Wire vs Reg in Verilog: Key Differences and Usage

In Verilog, wire represents a physical connection used for continuous assignments and driven by combinational logic, while reg holds values assigned inside procedural blocks and models storage elements like flip-flops. wire cannot store values, but reg can retain values until changed.

Quick Comparison

This table summarizes the main differences between wire and reg in Verilog.

Aspect	wire	reg
Purpose	Represents physical connections, driven by continuous assignments	Stores values assigned in procedural blocks
Value Storage	Does not store value; reflects driven signal	Stores value until explicitly changed
Assignment Type	Continuous assignment using assign	Procedural assignment inside always or initial blocks
Usage	Used for combinational logic wiring	Used for variables and storage elements
Default Value	Undefined (Z or X) if not driven	Retains last assigned value or undefined if never assigned
Can be on Left Side of assign	Yes	No

Key Differences

wire is used to model physical connections in hardware. It cannot hold a value by itself and must be driven by something like a continuous assign statement or an output of a module. This makes it ideal for representing combinational signals that change immediately when inputs change.

On the other hand, reg is a data type that can store values and is typically assigned inside procedural blocks such as always or initial. It models storage elements like flip-flops or latches in hardware, holding its value until explicitly updated.

In summary, use wire for connections and combinational logic outputs, and use reg for variables that need to remember values across simulation time steps or clock cycles.

Code Comparison

Here is an example showing how to implement a simple combinational AND gate using wire with continuous assignment.

verilog

module and_gate_wire(input a, input b, output wire y);
  assign y = a & b;
endmodule

Reg Equivalent

The same AND gate behavior can be implemented using reg inside an always block, which is procedural.

verilog

module and_gate_reg(input a, input b, output reg y);
  always @(*) begin
    y = a & b;
  end
endmodule

When to Use Which

Choose wire when you need to represent simple connections or combinational logic outputs driven by continuous assignments. It is the natural choice for signals that do not store state.

Choose reg when you need to store values, such as in sequential logic or when assigning values inside procedural blocks like always. Use reg for variables that must hold their value until updated.

Key Takeaways

wire models physical connections and cannot store values.

reg stores values and is assigned inside procedural blocks.

Use wire for combinational logic and continuous assignments.

Use reg for variables that hold state or are assigned in always blocks.

Choosing the right type ensures correct hardware behavior and simulation.