Signed vs Unsigned in Verilog: Key Differences and Usage

In Verilog, signed variables can represent both positive and negative numbers using two's complement, while unsigned variables represent only non-negative numbers. This distinction affects arithmetic operations and comparisons, as signed variables consider the sign bit, but unsigned do not.

Quick Comparison

This table summarizes the main differences between signed and unsigned types in Verilog.

Aspect	Signed	Unsigned
Value Range	Can be positive or negative (two's complement)	Only non-negative (zero and positive)
Default Type	Must be declared explicitly	Default if not declared signed
Arithmetic	Considers sign bit in operations	Treats all bits as magnitude
Comparison	Signed comparisons consider sign	Comparisons do not consider sign bit
Use Case	For values that can be negative	For values that are always zero or positive

Key Differences

In Verilog, signed and unsigned keywords define how the bits of a variable are interpreted. A signed variable uses the most significant bit as a sign bit, allowing it to represent negative numbers using two's complement notation. This means arithmetic operations like addition, subtraction, and comparisons will correctly handle negative values.

On the other hand, unsigned variables treat all bits as part of a positive number. Arithmetic and comparisons on unsigned variables do not consider any sign bit, so they only represent zero or positive values. By default, Verilog treats variables as unsigned unless declared otherwise.

Because of these differences, mixing signed and unsigned variables in expressions can lead to unexpected results if not handled carefully. It is important to declare variables as signed when negative values are expected and to be mindful of how operations behave with each type.

Code Comparison

Here is an example showing how a signed variable handles negative numbers in arithmetic.

verilog

module signed_example;
  reg signed [3:0] a = -3; // 4-bit signed number
  reg signed [3:0] b = 2;
  reg signed [4:0] result;

  initial begin
    result = a + b;
    $display("Signed: %d + %d = %d", a, b, result);
  end
endmodule

Output

Signed: -3 + 2 = -1

Unsigned Equivalent

The same arithmetic with unsigned variables treats all bits as positive values.

verilog

module unsigned_example;
  reg [3:0] a = 4'b1101; // 13 in decimal
  reg [3:0] b = 2;
  reg [4:0] result;

  initial begin
    result = a + b;
    $display("Unsigned: %d + %d = %d", a, b, result);
  end
endmodule

Output

Unsigned: 13 + 2 = 15

When to Use Which

Choose signed when your values can be negative or when you need correct signed arithmetic and comparisons. This is common in calculations involving differences, offsets, or signed data.

Choose unsigned when your values are always zero or positive, such as counters, addresses, or bit masks. Using unsigned can simplify logic and avoid sign-related issues.

Always be explicit about signedness to avoid bugs, especially when mixing variables in expressions.

Key Takeaways

Signed variables in Verilog represent negative and positive numbers using two's complement.

Unsigned variables represent only zero or positive numbers and ignore sign bits.

Arithmetic and comparisons behave differently for signed vs unsigned types.

Declare variables explicitly as signed when negative values are expected.

Use unsigned for counters, addresses, and always-positive values.