Verilog Code for Subtractor: Syntax and Example

A subtractor in Verilog can be created using the - operator inside an always block or continuous assignment. For example, assign diff = a - b; subtracts two inputs a and b and outputs the result diff.

Syntax

The basic syntax for a subtractor in Verilog uses the subtraction operator -. You can implement it using a continuous assignment or inside an always block for sequential logic.

• Continuous assignment: assign result = a - b; subtracts b from a and assigns it to result.
• Procedural block: Inside an always block, you can write result = a - b; to perform subtraction on signals.

verilog

module subtractor(
    input wire [3:0] a,
    input wire [3:0] b,
    output wire [3:0] diff
);

assign diff = a - b;

endmodule

Example

This example shows a simple 4-bit subtractor module that subtracts input b from a and outputs the difference diff. It uses continuous assignment for combinational subtraction.

verilog

module subtractor(
    input wire [3:0] a,
    input wire [3:0] b,
    output wire [3:0] diff
);

assign diff = a - b;

endmodule

// Testbench
module testbench();
    reg [3:0] a, b;
    wire [3:0] diff;

    subtractor uut(.a(a), .b(b), .diff(diff));

    initial begin
        a = 4'd9; b = 4'd5;
        #10;
        $display("a = %d, b = %d, diff = %d", a, b, diff);

        a = 4'd3; b = 4'd7;
        #10;
        $display("a = %d, b = %d, diff = %d", a, b, diff);

        $finish;
    end
endmodule

Output

a = 9, b = 5, diff = 4
a = 3, b = 7, diff = 12

Common Pitfalls

Common mistakes when writing a subtractor in Verilog include:

• Not handling underflow or borrow correctly, which can cause unexpected results for unsigned numbers.
• Using signed and unsigned types inconsistently, leading to wrong subtraction results.
• Forgetting to declare inputs and outputs with correct bit widths.

Always check if your inputs are signed or unsigned and choose the right data type.

verilog

/* Wrong: mixing signed and unsigned without declaration */
module wrong_subtractor(
    input [3:0] a,
    input signed [3:0] b,
    output [3:0] diff
);
    assign diff = a - b; // May cause unexpected results
endmodule

/* Right: declare both as signed if negative values expected */
module correct_subtractor(
    input signed [3:0] a,
    input signed [3:0] b,
    output signed [3:0] diff
);
    assign diff = a - b;
endmodule

Quick Reference

Tips for writing subtractors in Verilog:

• Use assign result = a - b; for simple combinational subtractors.
• Declare inputs and outputs with correct bit widths.
• Use signed keyword if negative numbers are involved.
• Test with different values to check underflow or borrow behavior.

Key Takeaways

Use the subtraction operator '-' inside an assign statement or always block to create a subtractor.

Declare inputs and outputs with correct bit widths and use 'signed' if negative values are needed.

Test your subtractor with various inputs to ensure correct behavior, especially for underflow.

Avoid mixing signed and unsigned types to prevent unexpected results.

Continuous assignment is the simplest way to implement a combinational subtractor.