Verilog Code for Divider: Syntax and Example

In Verilog, a divider can be created using the / operator inside an always block or as a continuous assignment. The divider module takes two inputs (dividend and divisor) and outputs the quotient and optionally the remainder.

Syntax

The basic syntax for a divider in Verilog uses the division operator /. You can implement it inside an always block or as a continuous assignment. The inputs are usually two numbers: dividend and divisor. The output is the quotient. Optionally, you can also output the remainder using the modulus operator %.

• input [width-1:0] dividend: Number to be divided.
• input [width-1:0] divisor: Number to divide by.
• output [width-1:0] quotient: Result of division.
• output [width-1:0] remainder: Remainder after division (optional).

verilog

module divider(
    input  wire [7:0] dividend,
    input  wire [7:0] divisor,
    output reg  [7:0] quotient,
    output reg  [7:0] remainder
);

always @(*) begin
    quotient  = dividend / divisor;
    remainder = dividend % divisor;
end

endmodule

Example

This example shows a simple divider module that divides two 8-bit numbers and outputs the quotient and remainder. It uses combinational logic with an always @(*) block to update outputs whenever inputs change.

verilog

module test_divider;
    reg  [7:0] dividend;
    reg  [7:0] divisor;
    wire [7:0] quotient;
    wire [7:0] remainder;

    divider uut (
        .dividend(dividend),
        .divisor(divisor),
        .quotient(quotient),
        .remainder(remainder)
    );

    initial begin
        dividend = 100;
        divisor = 7;
        #10;
        $display("Dividend: %d, Divisor: %d", dividend, divisor);
        $display("Quotient: %d", quotient);
        $display("Remainder: %d", remainder);
        $finish;
    end
endmodule

module divider(
    input  wire [7:0] dividend,
    input  wire [7:0] divisor,
    output reg  [7:0] quotient,
    output reg  [7:0] remainder
);

always @(*) begin
    quotient  = dividend / divisor;
    remainder = dividend % divisor;
end

endmodule

Output

Dividend: 100, Divisor: 7
Quotient: 14
Remainder: 2

Common Pitfalls

Common mistakes when writing a divider in Verilog include:

• Dividing by zero, which causes simulation errors or undefined behavior.
• Using blocking assignments = incorrectly in sequential logic instead of non-blocking <=.
• Not handling the remainder if needed.
• Assuming division is always fast; hardware dividers can be slow or resource-heavy.

Always check divisor is not zero before dividing.

verilog

module safe_divider(
    input  wire [7:0] dividend,
    input  wire [7:0] divisor,
    output reg  [7:0] quotient,
    output reg  [7:0] remainder
);

always @(*) begin
    if (divisor == 0) begin
        quotient  = 8'b0;  // or some error code
        remainder = 8'b0;
    end else begin
        quotient  = dividend / divisor;
        remainder = dividend % divisor;
    end
end

endmodule

Quick Reference

Tips for writing dividers in Verilog:

• Use / for division and % for remainder.
• Check divisor is not zero to avoid errors.
• Use combinational always @(*) for simple dividers.
• For large or signed division, consider dedicated divider IP or algorithms.

Key Takeaways

Use the division operator '/' inside an always block or continuous assignment for division in Verilog.

Always check that the divisor is not zero to prevent simulation errors.

You can also get the remainder using the modulus operator '%'.

Simple dividers can be combinational, but large dividers may need special hardware or algorithms.

Use non-blocking assignments in sequential logic and blocking assignments in combinational logic.