What is State Diagram in Verilog: Explanation and Example

A state diagram in Verilog is a visual representation of a finite state machine (FSM) showing states and transitions based on inputs. It helps design and understand sequential logic by mapping how the system moves from one state to another in response to signals.

How It Works

A state diagram is like a map for a machine that can be in different conditions called states. Imagine a traffic light that changes from green to yellow to red. Each color is a state, and the arrows show when and how it changes.

In Verilog, this map guides the code for a finite state machine (FSM). The FSM stores the current state and changes it based on inputs and rules. The state diagram helps programmers plan these changes clearly before writing code.

Example

This example shows a simple FSM with two states: IDLE and ACTIVE. The FSM switches states when the input signal start changes.

verilog

module simple_fsm(
    input wire clk,
    input wire reset,
    input wire start,
    output reg state
);

    // State encoding
    localparam IDLE = 1'b0;
    localparam ACTIVE = 1'b1;

    reg current_state, next_state;

    // State register
    always @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= IDLE;
        else
            current_state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case (current_state)
            IDLE: next_state = start ? ACTIVE : IDLE;
            ACTIVE: next_state = start ? ACTIVE : IDLE;
            default: next_state = IDLE;
        endcase
    end

    // Output logic
    always @(*) begin
        state = current_state;
    end

endmodule

When to Use

Use state diagrams in Verilog when designing circuits that have multiple steps or modes, like controllers, communication protocols, or user interfaces. They help you visualize how your system behaves over time and make coding easier and less error-prone.

For example, a vending machine controller uses a state diagram to manage coin insertion, selection, and dispensing. This ensures the machine reacts correctly to each input in order.

Key Points

• A state diagram shows states and transitions in a finite state machine.
• It helps plan and understand sequential logic in Verilog.
• States represent conditions; transitions happen on inputs or events.
• Verilog code uses state diagrams to implement FSMs with registers and logic.
• Useful for designing controllers, protocols, and complex digital systems.

Key Takeaways

A state diagram visually maps states and transitions for a finite state machine in Verilog.

It simplifies designing and understanding sequential logic circuits.

Use state diagrams to plan FSM behavior before coding in Verilog.

Verilog FSM code uses registers to hold states and logic to decide transitions.

State diagrams are essential for controllers, protocols, and multi-step processes.