Verilog Code for Encoder: Syntax, Example, and Tips

A Verilog encoder converts multiple input lines into a binary code output. Use always blocks with case statements to detect which input is active and assign the corresponding binary output code. This simple structure efficiently encodes inputs into fewer output bits.

Syntax

An encoder in Verilog typically uses an always block triggered by input changes. Inside, a case statement checks which input line is active (usually one-hot) and assigns a binary code to the output.

The main parts are:

• Inputs: Multiple input lines (e.g., 4 inputs)
• Output: Binary code representing the active input
• always @(*): Runs whenever inputs change
• case statement: Matches input pattern to output code

verilog

module encoder(
    input wire [3:0] in,
    output reg [1:0] out
);

always @(*) begin
    case (in)
        4'b0001: out = 2'b00;
        4'b0010: out = 2'b01;
        4'b0100: out = 2'b10;
        4'b1000: out = 2'b11;
        default: out = 2'b00; // default output
    endcase
end

endmodule

Example

This example shows a 4-to-2 encoder. It converts one active input line among four into a 2-bit binary output. If input in[2] is high, output will be 2'b10.

verilog

module encoder(
    input wire [3:0] in,
    output reg [1:0] out
);

always @(*) begin
    case (in)
        4'b0001: out = 2'b00;
        4'b0010: out = 2'b01;
        4'b0100: out = 2'b10;
        4'b1000: out = 2'b11;
        default: out = 2'b00;
    endcase
end

endmodule

// Testbench
module test_encoder;
    reg [3:0] in;
    wire [1:0] out;

    encoder uut(.in(in), .out(out));

    initial begin
        in = 4'b0001; #10;
        $display("Input: %b, Output: %b", in, out);
        in = 4'b0010; #10;
        $display("Input: %b, Output: %b", in, out);
        in = 4'b0100; #10;
        $display("Input: %b, Output: %b", in, out);
        in = 4'b1000; #10;
        $display("Input: %b, Output: %b", in, out);
        in = 4'b0000; #10;
        $display("Input: %b, Output: %b", in, out);
        $finish;
    end
endmodule

Output

Input: 0001, Output: 00
Input: 0010, Output: 01
Input: 0100, Output: 10
Input: 1000, Output: 11
Input: 0000, Output: 00

Common Pitfalls

Common mistakes when writing encoders include:

• Not handling the case when no inputs are active, which can cause unexpected outputs.
• Multiple inputs active at once, which breaks the one-hot assumption and leads to incorrect encoding.
• Using blocking assignments (=) inside always @(*) blocks instead of non-blocking (<=) can cause simulation mismatches.

Always ensure inputs are one-hot and provide a default case to avoid latches.

verilog

/* Wrong: Missing default case and multiple active inputs not handled */
always @(*) begin
    case (in)
        4'b0001: out = 2'b00;
        4'b0010: out = 2'b01;
        4'b0100: out = 2'b10;
        4'b1000: out = 2'b11;
    endcase
end

/* Right: Added default and check for multiple active inputs */
always @(*) begin
    if (in == 4'b0001) out = 2'b00;
    else if (in == 4'b0010) out = 2'b01;
    else if (in == 4'b0100) out = 2'b10;
    else if (in == 4'b1000) out = 2'b11;
    else out = 2'b00; // default safe output
end

Quick Reference

Tips for writing Verilog encoders:

• Use always @(*) for combinational logic.
• Use case or if-else to detect active inputs.
• Ensure inputs are one-hot (only one input active at a time).
• Always include a default case to avoid latches.
• Test with all input combinations including no input active.

Key Takeaways

Use an always block with a case statement to encode one-hot inputs into binary outputs.

Always include a default case to handle unexpected input patterns safely.

Ensure only one input is active at a time to avoid incorrect encoding.

Test your encoder with all input combinations including no active inputs.

Use non-blocking assignments inside always blocks for predictable simulation.