Verilog Code for Sequence Detector 1011: Complete Example

A sequence detector for 1011 in Verilog uses a finite state machine to track input bits and output a signal when the pattern is detected. The code defines states for each step of the pattern and transitions based on input bits, setting the output high when the full sequence is matched.

Syntax

The sequence detector uses a finite state machine (FSM) with states representing how much of the pattern has been matched so far. The main parts are:

• module: Defines the Verilog module with inputs and outputs.
• input clk, reset, in_bit: Clock, reset, and input bit signals.
• output reg detected: Output signal set high when sequence is found.
• state and next_state: Variables to hold current and next FSM states.
• always @(posedge clk or posedge reset): Synchronous block to update state on clock or reset.
• case statement: Defines transitions between states based on input bit.

verilog

module seq_detector_1011(input clk, reset, in_bit, output reg detected);
  typedef enum reg [2:0] {S0, S1, S2, S3, S4} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    detected = 0;
    case(state)
      S0: if (in_bit) next_state = S1; else next_state = S0;
      S1: if (!in_bit) next_state = S2; else next_state = S1;
      S2: if (in_bit) next_state = S3; else next_state = S0;
      S3: if (in_bit) begin
            next_state = S4;
            detected = 1;
          end else next_state = S2;
      S4: if (in_bit) next_state = S1; else next_state = S2;
      default: next_state = S0;
    endcase
  end
endmodule

Example

This example shows a complete Verilog module for detecting the sequence 1011. It outputs detected = 1 when the pattern is found in the input stream. The FSM resets on reset and updates on the rising edge of clk.

verilog

module seq_detector_1011(input clk, reset, in_bit, output reg detected);
  typedef enum reg [2:0] {S0, S1, S2, S3, S4} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    detected = 0;
    case(state)
      S0: if (in_bit) next_state = S1; else next_state = S0;
      S1: if (!in_bit) next_state = S2; else next_state = S1;
      S2: if (in_bit) next_state = S3; else next_state = S0;
      S3: if (in_bit) begin
            next_state = S4;
            detected = 1;
          end else next_state = S2;
      S4: if (in_bit) next_state = S1; else next_state = S2;
      default: next_state = S0;
    endcase
  end
endmodule

Output

No direct console output; the signal 'detected' goes high when sequence 1011 is detected on input 'in_bit'.

Common Pitfalls

Common mistakes when writing a sequence detector include:

• Not handling overlapping sequences properly, which causes missed detections.
• Forgetting to reset the FSM state on reset signal.
• Incorrect state transitions that do not follow the pattern logic.
• Setting the output signal detected only in the state update block instead of combinational logic, causing glitches.

Always use a separate combinational block for next state and output logic to avoid timing issues.

verilog

/* Wrong way: output assigned in sequential block causing glitches */
always @(posedge clk or posedge reset) begin
  if (reset) begin
    state <= S0;
    detected <= 0;
  end else begin
    state <= next_state;
    if (state == S3 && in_bit == 1) detected <= 1; else detected <= 0;
  end
end

/* Right way: output assigned in combinational block */
always @(*) begin
  detected = 0;
  case(state)
    S3: if (in_bit) detected = 1;
    default: detected = 0;
  endcase
end

Quick Reference

• States: Represent progress in matching 1011.
• Input: Single bit stream checked each clock.
• Output: High when full sequence detected.
• Reset: Initializes FSM to start state.
• Overlap: FSM allows overlapping sequences detection.

Key Takeaways

Use a finite state machine with states representing partial matches of 1011.

Assign output signals in combinational logic to avoid glitches.

Reset the FSM state properly to ensure correct operation.

Handle overlapping sequences by carefully designing state transitions.

Test the design with different input sequences to verify detection.