Wire vs Reg in Verilog: Key Differences and Usage

In Verilog, wire represents a physical connection and is used for continuous assignments, while reg holds values and is used in procedural blocks like always. wire cannot store values, but reg can retain values until changed.

Quick Comparison

This table summarizes the main differences between wire and reg in Verilog.

Factor	wire	reg
Type	Represents a physical connection	Stores value in procedural blocks
Assignment	Continuous assignment using assign	Procedural assignment inside always or initial blocks
Value Storage	Does not store value, reflects input	Stores value until explicitly changed
Usage	Used for connecting modules and combinational logic	Used for variables in sequential logic or procedural code
Default Value	Undefined until driven	Retains last assigned value
Driving Source	Driven by continuous drivers	Driven by procedural statements

Key Differences

wire is used to model physical wires in hardware. It cannot hold a value by itself and must be driven by something like an assign statement or output of a module. It continuously reflects the value driven onto it, making it ideal for combinational logic connections.

On the other hand, reg is a data type that can store values. It is used inside procedural blocks such as always or initial to hold values over time, similar to variables in software. This makes reg suitable for modeling flip-flops or latches where the value must be remembered until updated.

In summary, wire is for connections and continuous assignments, while reg is for variables that hold state in procedural code.

Code Comparison

verilog

module wire_example(input a, input b, output c);
  // wire used with continuous assignment
  wire temp;
  assign temp = a & b;
  assign c = temp | a;
endmodule

reg Equivalent

verilog

module reg_example(input a, input b, output reg c);
  // reg used inside procedural block
  always @(*) begin
    c = (a & b) | a;
  end
endmodule

When to Use Which

Choose wire when you need to represent simple connections or combinational logic driven by continuous assignments or module outputs. Use reg when you need to store values inside procedural blocks, such as modeling sequential logic or variables that change based on events.

In short, wire is for connections and reg is for storage and procedural assignments.

Key Takeaways

wire is for continuous connections and cannot store values.

reg stores values and is used inside procedural blocks like always.

Use wire for combinational logic connections and reg for sequential logic or variables.

wire assignments use assign, reg assignments happen inside procedural blocks.

Choosing the right type ensures correct hardware behavior and simulation.