How to Instantiate Module in Verilog: Syntax and Examples
To instantiate a module in Verilog, use the syntax
module_name instance_name (port_connections); where module_name is the module you want to use, and instance_name is a unique name for this instance. Connect ports by position or by name inside the parentheses.Syntax
The basic syntax to instantiate a module in Verilog is:
- module_name: The name of the module you want to use.
- instance_name: A unique name for this instance of the module.
- port_connections: The signals connected to the module's ports, either by position or by name.
Example of positional connection:
module_name instance_name (signal1, signal2, ...);
Example of named connection:
module_name instance_name (.port1(signal1), .port2(signal2), ...);
verilog
module_name instance_name (port1, port2, ...);
Example
This example shows how to instantiate a simple and_gate module inside a top-level module. It demonstrates both positional and named port connections.
verilog
module and_gate(input a, input b, output y); assign y = a & b; endmodule module top_module(); wire x, z, out1, out2; assign x = 1'b1; assign z = 1'b0; // Positional instantiation and_gate and1 (x, z, out1); // Named instantiation and_gate and2 (.a(x), .b(z), .y(out2)); endmodule
Common Pitfalls
Common mistakes when instantiating modules include:
- Using the same instance_name more than once, which causes conflicts.
- Mixing positional and named port connections incorrectly.
- Not matching the order of ports in positional connections.
- Forgetting the dot
.before port names in named connections.
Example of wrong and right ways:
verilog
// Wrong: Missing dot before port names in named connection and_gate and_wrong (a(x), b(z), y(out)); // Right: Correct named connection with dots and_gate and_right (.a(x), .b(z), .y(out));
Quick Reference
| Concept | Description | Example |
|---|---|---|
| Module Name | Name of the module to instantiate | and_gate |
| Instance Name | Unique name for this instance | and1 |
| Positional Connection | Connect ports by order | and_gate and1 (a, b, y); |
| Named Connection | Connect ports by name | and_gate and2 (.a(a), .b(b), .y(y)); |
| Port Connection | Signals connected to ports | a, b, y |
Key Takeaways
Instantiate a module using
module_name instance_name (port_connections); syntax.Use positional or named port connections carefully to match module ports.
Always give each instance a unique name to avoid conflicts.
Named connections use a dot before port names like
.port(signal).Check port order in positional connections to prevent wiring errors.