Verilog Code for 4-to-1 Multiplexer: Syntax and Example

A 4-to-1 multiplexer in Verilog selects one of four inputs based on two select lines using case or if-else statements inside an always block. The output reflects the selected input based on the select signals.

Syntax

The basic syntax for a 4-to-1 multiplexer uses an always block triggered by changes in inputs or select lines. Inside, a case statement chooses the output based on the 2-bit select signal.

• input [3:0] in: Four data inputs.
• input [1:0] sel: Two-bit select signal to choose which input to output.
• output reg out: Output signal reflecting the selected input.

verilog

module mux4to1(
    input [3:0] in,
    input [1:0] sel,
    output reg out
);

always @(*) begin
    case(sel)
        2'b00: out = in[0];
        2'b01: out = in[1];
        2'b10: out = in[2];
        2'b11: out = in[3];
        default: out = 1'b0;
    endcase
end

endmodule

Example

This example shows a complete 4-to-1 multiplexer module and a testbench that applies different select signals and inputs. It demonstrates how the output changes according to the select lines.

verilog

module mux4to1(
    input [3:0] in,
    input [1:0] sel,
    output reg out
);

always @(*) begin
    case(sel)
        2'b00: out = in[0];
        2'b01: out = in[1];
        2'b10: out = in[2];
        2'b11: out = in[3];
        default: out = 1'b0;
    endcase
end

endmodule

module testbench();
    reg [3:0] in;
    reg [1:0] sel;
    wire out;

    mux4to1 uut(.in(in), .sel(sel), .out(out));

    initial begin
        in = 4'b1010; // Inputs: in[3]=1, in[2]=0, in[1]=1, in[0]=0

        sel = 2'b00; #10;
        $display("sel=00, out=%b (expected 0)", out);

        sel = 2'b01; #10;
        $display("sel=01, out=%b (expected 1)", out);

        sel = 2'b10; #10;
        $display("sel=10, out=%b (expected 0)", out);

        sel = 2'b11; #10;
        $display("sel=11, out=%b (expected 1)", out);

        $finish;
    end
endmodule

Output

sel=00, out=0 (expected 0)
sel=01, out=1 (expected 1)
sel=10, out=0 (expected 0)
sel=11, out=1 (expected 1)

Common Pitfalls

Common mistakes when writing a 4-to-1 multiplexer in Verilog include:

• Not using reg type for the output when assigned inside an always block.
• Forgetting to cover all select cases, which can cause latches or unintended behavior.
• Using blocking assignments (=) incorrectly in sequential logic (though for combinational always @(*), blocking is fine).
• Not using default in case statements, which can lead to simulation mismatches.

Example of a wrong approach and the corrected version:

verilog

// Wrong: output not declared as reg and no default case
module mux4to1_wrong(
    input [3:0] in,
    input [1:0] sel,
    output out
);

always @(*) begin
    case(sel)
        2'b00: out = in[0];
        2'b01: out = in[1];
        2'b10: out = in[2];
        2'b11: out = in[3];
    endcase
end

endmodule

// Corrected version
module mux4to1_correct(
    input [3:0] in,
    input [1:0] sel,
    output reg out
);

always @(*) begin
    case(sel)
        2'b00: out = in[0];
        2'b01: out = in[1];
        2'b10: out = in[2];
        2'b11: out = in[3];
        default: out = 1'b0;
    endcase
end

endmodule

Quick Reference

• Use always @(*) for combinational logic.
• Declare output as reg if assigned inside always block.
• Use a case statement with all select values covered.
• Include a default case to avoid latches.
• Test with different inputs and select signals to verify behavior.

Key Takeaways

A 4-to-1 multiplexer selects one of four inputs based on two select bits using a case statement inside an always block.

Declare the output as reg when assigning it inside an always block for combinational logic.

Always cover all select cases and include a default case to avoid unintended latches.

Use always @(*) to ensure the output updates whenever inputs or select signals change.

Test your multiplexer with different inputs and select values to confirm correct output.