How to Use Xilinx Vivado for Verilog: Step-by-Step Guide

To use Xilinx Vivado for Verilog, start by creating a new project in Vivado, add your Verilog source files, then run simulation and synthesis inside the tool. Vivado provides an integrated environment to write, test, and implement your Verilog designs on Xilinx FPGAs.

Syntax

In Vivado, Verilog code is written in standard Verilog syntax. You create modules with inputs and outputs, define internal logic, and use procedural blocks for behavior.

Key parts include:

• module: Defines a hardware block.
• input/output: Declare signals coming in or out.
• assign: For continuous assignments.
• always: For procedural logic triggered by events.
• endmodule: Ends the module definition.

verilog

module simple_and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

Example

This example shows a simple AND gate module in Verilog. You can add this code to Vivado, simulate it, and synthesize it for FPGA implementation.

verilog

module simple_and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

// Testbench to simulate the AND gate
module testbench();
  reg a, b;
  wire y;
  simple_and_gate uut(.a(a), .b(b), .y(y));

  initial begin
    a = 0; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 0;
    #10 a = 1; b = 1;
    #10 $finish;
  end

  initial begin
    $monitor("At time %t: a=%b b=%b y=%b", $time, a, b, y);
  end
endmodule

Output

At time 0: a=0 b=0 y=0
At time 10: a=0 b=1 y=0
At time 20: a=1 b=0 y=0
At time 30: a=1 b=1 y=1

Common Pitfalls

Common mistakes when using Vivado for Verilog include:

• Not setting the top module correctly in the project, causing synthesis errors.
• Forgetting to add all source files to the project.
• Using blocking (=) vs non-blocking (<=) assignments incorrectly in always blocks.
• Not running simulation before synthesis to catch logic errors.

Always verify your design with simulation and check Vivado's messages for warnings or errors.

verilog

/* Wrong: Using blocking assignment in sequential logic */
module wrong_example(input clk, input d, output reg q);
  always @(posedge clk) begin
    q = d; // blocking assignment causes timing issues
  end
endmodule

/* Correct: Use non-blocking assignment for sequential logic */
module correct_example(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d; // non-blocking assignment is correct
  end
endmodule

Quick Reference

Tips for using Vivado with Verilog:

• Create a new RTL project and select the correct FPGA device.
• Add all Verilog source and testbench files to the project.
• Set the top module before synthesis.
• Use Vivado's built-in simulator to run testbenches.
• Check synthesis reports for resource usage and timing.
• Generate bitstream to program the FPGA.

Key Takeaways

Start by creating a Vivado project and adding your Verilog files.

Write Verilog modules using standard syntax with inputs, outputs, and logic.

Simulate your design in Vivado before synthesis to catch errors early.

Set the correct top module and add all source files to avoid build issues.

Use non-blocking assignments in sequential logic for correct behavior.