Full Case and Parallel Case in Verilog: Explanation and Examples

In Verilog, full_case means a case statement covers all possible input values, so no default is needed. parallel_case means the case items are mutually exclusive, allowing the compiler to optimize by checking cases in parallel.

How It Works

Think of a case statement like a traffic controller directing cars based on their color. A full case means the controller has instructions for every possible car color, so no car is left without direction. This means the case covers all input values explicitly, and no default action is needed.

A parallel case means the controller knows that each car color is unique and does not overlap with others. So, the controller can check all colors at once instead of one by one. In Verilog, this means the case items are mutually exclusive, allowing the hardware synthesis tool to optimize the logic by evaluating all cases in parallel.

Example

This example shows a case statement that is both full and parallel. It covers all 2-bit input values (00, 01, 10, 11) with no default, and each case is unique.

verilog

module full_parallel_case(input [1:0] sel, output reg [1:0] out);
  always @(*) begin
    case (sel) // synthesis full_case parallel_case
      2'b00: out = 2'b01;
      2'b01: out = 2'b10;
      2'b10: out = 2'b11;
      2'b11: out = 2'b00;
    endcase
  end
endmodule

When to Use

Use full_case when you know all possible input values and want to avoid unintended latches or incomplete logic. It helps synthesis tools generate safer and more predictable hardware.

Use parallel_case when your case items do not overlap and you want to enable the synthesis tool to optimize the logic for speed by checking all cases simultaneously. This is common in state machines or multiplexers where inputs are distinct.

Key Points

• Full case means all input values are covered explicitly.
• Parallel case means case items are mutually exclusive.
• Both help synthesis tools optimize hardware.
• Use full_case and parallel_case pragmas to guide synthesis.
• Missing cases or overlaps can cause unintended hardware behavior.

Key Takeaways

Full case covers every possible input value in a case statement.

Parallel case means case items do not overlap and are mutually exclusive.

Using full_case and parallel_case helps synthesis tools optimize hardware.

Always ensure your case statements are complete to avoid unintended latches.

Parallel case is useful for distinct input conditions like state machines.