How to Compile and Run Verilog Code: Step-by-Step Guide

To compile and run Verilog code, use a simulator like Icarus Verilog. Compile your .v file with iverilog -o output_file input_file.v and then run the simulation with vvp output_file.

Syntax

Here is the basic syntax to compile and run Verilog code using Icarus Verilog:

• iverilog -o <output_file> <input_file.v>: Compiles the Verilog source file into an executable simulation file.
• vvp <output_file>: Runs the compiled simulation file.

The -o option specifies the name of the output executable file. The input file is your Verilog source code with a .v extension.

bash

iverilog -o my_simulation testbench.v
vvp my_simulation

Example

This example shows a simple Verilog module and a testbench to simulate it. The commands compile and run the simulation, printing output from the testbench.

verilog

`timescale 1ns/1ps
module and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

module testbench;
  reg a, b;
  wire y;

  and_gate uut(.a(a), .b(b), .y(y));

  initial begin
    $monitor("At time %t: a=%b b=%b y=%b", $time, a, b, y);
    a = 0; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 0;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Output

At time 0: a=0 b=0 y=0
At time 10: a=0 b=1 y=0
At time 20: a=1 b=0 y=0
At time 30: a=1 b=1 y=1

Common Pitfalls

Common mistakes when compiling and running Verilog code include:

• Forgetting to specify the output file with -o, which causes the compiler to create a default file named a.out.
• Running vvp on the source file instead of the compiled output.
• Not including all necessary source files or testbenches in the compile command.
• Syntax errors in Verilog code that prevent successful compilation.

Always check compiler error messages carefully and ensure you run the correct commands in order.

bash

Wrong:
iverilog testbench.v
vvp testbench.v

Right:
iverilog -o testbench.out testbench.v
vvp testbench.out

Quick Reference

Command	Description
iverilog -o output_file input_file.v	Compile Verilog source to simulation executable
vvp output_file	Run the compiled simulation
$monitor	Print simulation signals during run
$finish	End simulation

Key Takeaways

Use 'iverilog -o output_file input_file.v' to compile Verilog code.

Run the simulation with 'vvp output_file' after compiling.

Include all source and testbench files in the compile command.

Check for syntax errors if compilation fails.

Use $monitor in testbenches to see signal changes during simulation.