Verilog Code for Array Multiplier: Syntax and Example

An array multiplier in Verilog multiplies two binary numbers using partial products arranged in an array and summed together. The code uses nested loops or generate blocks to create partial products and add them with full adders or simple addition. This approach models hardware multiplication clearly and efficiently.

Syntax

The basic syntax for an array multiplier module includes inputs for two binary numbers, an output for the product, and internal logic to generate and sum partial products. Typically, input and output ports are declared, and a for loop or generate block creates the partial products. Addition of these partial products is done using bitwise operations or adders.

• input [N-1:0] A, B; - The two numbers to multiply.
• output [2*N-1:0] P; - The product output.
• wire partial_products[][]; - Array to hold intermediate partial products.
• generate block or for loops to create partial products.
• Addition of partial products to form the final product.

verilog

module array_multiplier #(parameter N = 4) (
    input  [N-1:0] A,
    input  [N-1:0] B,
    output [2*N-1:0] P
);

    wire [N-1:0] partial_products [N-1:0];
    wire [2*N-1:0] sum [N-1:0];

    genvar i, j;

    // Generate partial products
    generate
        for (i = 0; i < N; i = i + 1) begin : gen_partial_products
            for (j = 0; j < N; j = j + 1) begin : gen_bits
                assign partial_products[i][j] = A[j] & B[i];
            end
        end
    endgenerate

    // Sum partial products shifted by i
    generate
        for (i = 0; i < N; i = i + 1) begin : gen_sum
            assign sum[i] = {{(N){1'b0}}, partial_products[i]} << i;
        end
    endgenerate

    // Add all sums to get product
    assign P = sum[0] + sum[1] + sum[2] + sum[3];

endmodule

Example

This example shows a 4-bit array multiplier module and a testbench that multiplies two 4-bit numbers. It demonstrates how partial products are generated and summed to produce the final 8-bit product.

verilog

module array_multiplier #(parameter N = 4) (
    input  [N-1:0] A,
    input  [N-1:0] B,
    output [2*N-1:0] P
);

    wire [N-1:0] partial_products [N-1:0];
    wire [2*N-1:0] sum [N-1:0];

    genvar i, j;

    generate
        for (i = 0; i < N; i = i + 1) begin : gen_partial_products
            for (j = 0; j < N; j = j + 1) begin : gen_bits
                assign partial_products[i][j] = A[j] & B[i];
            end
        end
    endgenerate

    generate
        for (i = 0; i < N; i = i + 1) begin : gen_sum
            assign sum[i] = {{(N){1'b0}}, partial_products[i]} << i;
        end
    endgenerate

    assign P = sum[0] + sum[1] + sum[2] + sum[3];

endmodule

module testbench();
    reg [3:0] A, B;
    wire [7:0] P;

    array_multiplier #(4) uut(.A(A), .B(B), .P(P));

    initial begin
        A = 4'b1011; // 11 decimal
        B = 4'b1101; // 13 decimal
        #10;
        $display("A = %b (%0d), B = %b (%0d), Product = %b (%0d)", A, A, B, B, P, P);
        $finish;
    end
endmodule

Output

A = 1011 (11), B = 1101 (13), Product = 10001111 (143)

Common Pitfalls

Common mistakes when writing an array multiplier in Verilog include:

• Not properly shifting partial products before summing, which leads to incorrect results.
• Forgetting to declare the correct width for the product output (should be twice the input width).
• Using blocking assignments (=) inside generate blocks instead of continuous assignments (assign).
• Not handling carry bits explicitly if using manual adders instead of the '+' operator.

Always verify bit widths and shifts carefully to avoid overflow or truncation.

verilog

/* Wrong: Missing shift of partial products */
assign sum[i] = {{(N){1'b0}}, partial_products[i]}; // No shift

/* Correct: Shift partial products by i */
assign sum[i] = {{(N){1'b0}}, partial_products[i]} << i;

Quick Reference

• Inputs: Two N-bit numbers.
• Output: 2N-bit product.
• Partial products: Generated by bitwise AND of each bit of multiplier and multiplicand.
• Summation: Shift partial products according to bit position and add.
• Use generate blocks: For scalable and clean code.

Key Takeaways

An array multiplier generates partial products by ANDing bits and sums them shifted by bit position.

Use a 2N-bit output to hold the full product of two N-bit inputs.

Shift partial products correctly before adding to avoid wrong results.

Use generate blocks for scalable and clean Verilog code.

Test with a simple testbench to verify multiplication correctness.