VerilogHow-ToBeginner · 4 min read

How to Pass Parameters to Module in Verilog: Syntax and Examples

In Verilog, you pass parameters to a module by declaring them with the parameter keyword inside the module and then overriding their values during module instantiation using the #() syntax. This allows you to customize module behavior without changing its internal code.

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Syntax

To pass parameters to a Verilog module, first declare parameters inside the module using the parameter keyword. When instantiating the module, override these parameters using the #() syntax before the instance name.

Parts explained:

parameter WIDTH = 8; sets a default parameter named WIDTH.
#(.WIDTH(16)) overrides the default WIDTH value to 16 during instantiation.
module_name instance_name (...); creates an instance of the module.

verilog

module my_module #(parameter WIDTH = 8) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

// Instantiation with parameter override
my_module #(.WIDTH(16)) instance_name (.in(some_input), .out(some_output));

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Example

This example shows a simple module with a parameter WIDTH that controls the bit width of input and output. The module is instantiated twice: once with the default width and once with an overridden width.

verilog

module pass_param #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

module testbench();
  reg [3:0] data1 = 4'b1010;
  wire [3:0] result1;

  reg [7:0] data2 = 8'b11001100;
  wire [7:0] result2;

  // Instance with default WIDTH = 4
  pass_param instance1 (.in(data1), .out(result1));

  // Instance with WIDTH overridden to 8
  pass_param #(.WIDTH(8)) instance2 (.in(data2), .out(result2));

  initial begin
    $display("Result1 (default WIDTH=4): %b", result1);
    $display("Result2 (overridden WIDTH=8): %b", result2);
  end
endmodule

Output

Result1 (default WIDTH=4): 1010 Result2 (overridden WIDTH=8): 11001100

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Common Pitfalls

Common mistakes when passing parameters include:

Forgetting the #() syntax before the instance name when overriding parameters.
Not matching parameter names exactly when overriding.
Trying to override parameters after the instance name or inside the port list, which is invalid.
Using parameters without default values and not overriding them, causing synthesis errors.

verilog

/* Wrong way: missing #() for parameter override */
// my_module .WIDTH(16) instance_name (.in(some_input), .out(some_output)); // Incorrect

/* Right way: use #() before instance name */
my_module #(.WIDTH(16)) instance_name (.in(some_input), .out(some_output));

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Quick Reference

Concept	Syntax Example	Description
Parameter Declaration	parameter WIDTH = 8;	Defines a default parameter inside a module.
Parameter Override	#(.WIDTH(16))	Overrides parameter value during module instantiation.
Module Instantiation	my_module #(.WIDTH(16)) inst (...);	Creates an instance with overridden parameters.
Default Parameter Use	parameter WIDTH = 8;	Allows module to work without override.
Port Declaration	input [WIDTH-1:0] in	Uses parameter to set port width.

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Key Takeaways

Declare parameters inside modules using the parameter keyword with default values.

Override parameters during instantiation using the #() syntax before the instance name.

Always match parameter names exactly when overriding to avoid errors.

Use default parameter values to make modules flexible and reusable.

Do not place parameter overrides inside the port list or after the instance name.