Verilog Code for Carry Lookahead Adder: Syntax and Example

A carry lookahead adder in Verilog uses generate and propagate signals to quickly compute carry bits, speeding up addition. The module typically takes two input vectors and a carry-in, then outputs the sum and carry-out using combinational logic.

Syntax

The carry lookahead adder module includes inputs for two numbers and a carry-in, outputs for sum and carry-out, and internal wires for generate (G) and propagate (P) signals. The carry signals are computed using these to speed up addition.

• Inputs: a, b (vectors), cin (carry in)
• Outputs: sum (result), cout (carry out)
• Internal: G (generate), P (propagate), C (carry signals)

verilog

module carry_lookahead_adder #(parameter N = 4) (
    input  wire [N-1:0] a, b,
    input  wire         cin,
    output wire [N-1:0] sum,
    output wire         cout
);

    wire [N-1:0] G; // Generate
    wire [N-1:0] P; // Propagate
    wire [N:0]   C; // Carry signals

    assign C[0] = cin;

    // Generate and propagate signals
    genvar i;
    generate
        for (i = 0; i < N; i = i + 1) begin : gp_loop
            assign G[i] = a[i] & b[i];
            assign P[i] = a[i] ^ b[i];
        end
    endgenerate

    // Carry lookahead logic
    generate
        for (i = 1; i <= N; i = i + 1) begin : carry_loop
            assign C[i] = G[i-1] | (P[i-1] & C[i-1]);
        end
    endgenerate

    // Sum calculation
    generate
        for (i = 0; i < N; i = i + 1) begin : sum_loop
            assign sum[i] = P[i] ^ C[i];
        end
    endgenerate

    assign cout = C[N];

endmodule

Example

This example shows a 4-bit carry lookahead adder module with inputs a, b, and cin. It outputs the 4-bit sum and carry-out. The testbench applies sample inputs and displays the results.

verilog

module testbench();
    reg [3:0] a, b;
    reg cin;
    wire [3:0] sum;
    wire cout;

    carry_lookahead_adder #(.N(4)) cla (
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .cout(cout)
    );

    initial begin
        $monitor("a=%b b=%b cin=%b | sum=%b cout=%b", a, b, cin, sum, cout);

        a = 4'b0011; b = 4'b0101; cin = 0; #10;
        a = 4'b1111; b = 4'b0001; cin = 1; #10;
        a = 4'b1010; b = 4'b0101; cin = 0; #10;
        a = 4'b0000; b = 4'b0000; cin = 0; #10;
        $finish;
    end
endmodule

Output

a=0011 b=0101 cin=0 | sum=0110 cout=0
a=1111 b=0001 cin=1 | sum=0001 cout=1
a=1010 b=0101 cin=0 | sum=1111 cout=0
a=0000 b=0000 cin=0 | sum=0000 cout=0

Common Pitfalls

Common mistakes include:

• Not initializing the carry-in signal C[0], which breaks carry propagation.
• Mixing up generate and propagate signals, causing incorrect carry logic.
• Forgetting to parameterize bit width, limiting reusability.
• Using blocking assignments (=) inside combinational logic instead of continuous assignments (assign).

verilog

/* Wrong: Missing carry-in initialization */
assign C[0] = 1'b0; // Should be assigned to input cin

/* Right: Correct carry-in initialization */
assign C[0] = cin;

Quick Reference

Tips for writing carry lookahead adders in Verilog:

• Use generate loops for scalable bit widths.
• Define generate (G) as a & b and propagate (P) as a ^ b.
• Calculate carry signals with C[i] = G[i-1] | (P[i-1] & C[i-1]).
• Sum bits are P[i] ^ C[i].
• Always connect the initial carry-in C[0] to the module input.

Key Takeaways

Carry lookahead adders speed up addition by computing carry signals in parallel using generate and propagate signals.

Use generate loops in Verilog to handle any bit width cleanly and efficiently.

Always initialize the carry-in signal correctly to ensure proper carry propagation.

Sum bits are computed by XORing propagate signals with their corresponding carry signals.

Avoid blocking assignments in combinational logic; use continuous assignments for correct behavior.