How to Model Multiplexer Using assign in Verilog

In Verilog, you can model a multiplexer using the assign statement by writing a conditional expression that selects one input based on the select signal. The syntax uses the ternary operator to choose between inputs, for example: assign out = sel ? in1 : in0;.

Syntax

The assign statement in Verilog is used for continuous assignments. For a multiplexer, it typically uses the ternary conditional operator ?: to select between inputs based on a select signal.

• assign: keyword to define a continuous assignment.
• out: output wire that gets the selected input.
• sel: select signal deciding which input to choose.
• in0, in1: input signals to select from.
• ?: ternary operator that returns in1 if sel is true, else in0.

verilog

assign out = sel ? in1 : in0;

Example

This example shows a 2-to-1 multiplexer modeled using assign. The output out selects between in0 and in1 based on the select signal sel.

verilog

module mux2to1(
    input wire in0,
    input wire in1,
    input wire sel,
    output wire out
);

assign out = sel ? in1 : in0;

endmodule

// Testbench to demonstrate mux behavior
module testbench();
    reg in0, in1, sel;
    wire out;

    mux2to1 uut(.in0(in0), .in1(in1), .sel(sel), .out(out));

    initial begin
        $display("sel in0 in1 | out");
        in0 = 0; in1 = 0; sel = 0; #10 $display(" %b   %b   %b |  %b", sel, in0, in1, out);
        in0 = 0; in1 = 1; sel = 0; #10 $display(" %b   %b   %b |  %b", sel, in0, in1, out);
        in0 = 1; in1 = 0; sel = 1; #10 $display(" %b   %b   %b |  %b", sel, in0, in1, out);
        in0 = 1; in1 = 1; sel = 1; #10 $display(" %b   %b   %b |  %b", sel, in0, in1, out);
        $finish;
    end
endmodule

Output

sel in0 in1 | out
 0   0   0 |  0
 0   0   1 |  0
 1   1   0 |  0
 1   1   1 |  1

Common Pitfalls

Common mistakes when modeling multiplexers with assign include:

• Using blocking assignments (=) inside assign which is not allowed.
• Forgetting to declare outputs as wire since assign works with wires.
• Incorrectly using multiple assign statements for the same output causing conflicts.
• Not handling all select signal cases in larger multiplexers, leading to latches.

verilog

/* Wrong: Using blocking assignment in assign */
// assign out = sel = in1 : in0; // Syntax error

/* Correct: Use ternary operator with assign */
assign out = sel ? in1 : in0;

Quick Reference

Tips for modeling multiplexers with assign:

• Use assign with ternary operator for simple muxes.
• Declare output as wire.
• For multiple inputs, nest ternary operators carefully.
• Test with all select signal values to avoid latches.

Key Takeaways

Use the assign statement with the ternary operator to model multiplexers simply.

Always declare outputs as wire when using assign.

Avoid multiple assign statements driving the same output to prevent conflicts.

Test all select signal cases to ensure correct multiplexer behavior.

Nested ternary operators can model multiplexers with more than two inputs.