Verilog Code for 2-to-1 Multiplexer: Syntax and Example

A 2-to-1 multiplexer in Verilog selects one of two inputs based on a select signal using assign or always blocks. The basic code uses a select input sel to choose between inputs in0 and in1 and outputs the selected input on out.

Syntax

The basic syntax for a 2-to-1 multiplexer in Verilog uses a module with inputs in0, in1, a select input sel, and an output out. The output is assigned based on the value of sel.

• module: Defines the multiplexer block.
• input: Declares input signals.
• output: Declares the output signal.
• assign: Continuously assigns the output based on the select signal.

verilog

module mux2to1(
    input wire in0,
    input wire in1,
    input wire sel,
    output wire out
);

assign out = sel ? in1 : in0;

endmodule

Example

This example shows a complete 2-to-1 multiplexer module and a testbench that applies different inputs and select signals. It demonstrates how the output changes according to the select input.

verilog

module mux2to1(
    input wire in0,
    input wire in1,
    input wire sel,
    output wire out
);

assign out = sel ? in1 : in0;

endmodule

module testbench();
    reg in0, in1, sel;
    wire out;

    mux2to1 uut(.in0(in0), .in1(in1), .sel(sel), .out(out));

    initial begin
        $monitor("Time=%0t | sel=%b | in0=%b | in1=%b | out=%b", $time, sel, in0, in1, out);

        in0 = 0; in1 = 0; sel = 0; #10;
        in0 = 0; in1 = 1; sel = 0; #10;
        in0 = 1; in1 = 0; sel = 1; #10;
        in0 = 1; in1 = 1; sel = 1; #10;
        $finish;
    end
endmodule

Output

Time=0 | sel=0 | in0=0 | in1=0 | out=0
Time=10 | sel=0 | in0=0 | in1=1 | out=0
Time=20 | sel=1 | in0=1 | in1=0 | out=0
Time=30 | sel=1 | in0=1 | in1=1 | out=1

Common Pitfalls

Common mistakes when coding a 2-to-1 multiplexer include:

• Forgetting to declare inputs and outputs correctly.
• Using blocking assignments (=) inside assign statements instead of continuous assignment.
• Not handling the select signal properly, causing incorrect output.
• Mixing combinational and sequential logic incorrectly.

Always use assign for simple combinational multiplexers or always @(*) blocks for more complex logic.

verilog

/* Wrong way: Using blocking assignment in assign statement */
// assign out = if(sel) in1 else in0; // Syntax error

/* Right way: Use ternary operator */
assign out = sel ? in1 : in0;

Quick Reference

Term	Description
in0, in1	Two data inputs to select from
sel	Select input (0 chooses in0, 1 chooses in1)
out	Output carrying selected input
assign	Continuous assignment for combinational logic
module	Defines the hardware block

Key Takeaways

Use the ternary operator in an assign statement to select between inputs based on sel.

Declare inputs and outputs clearly in the module header.

Test your multiplexer with different input and select values to verify behavior.

Avoid using procedural assignments inside continuous assign statements.

A 2-to-1 multiplexer outputs one of two inputs based on a single select signal.