Verilog Code for Pulse Generator: Syntax and Example

A pulse generator in Verilog can be created using a reg to hold the pulse signal and a clock-driven always block to toggle it for a specific duration. The pulse width and timing are controlled by counters inside the always block.

Syntax

A basic pulse generator uses a reg to store the pulse output and an always @(posedge clk) block to update the pulse based on a counter. The counter counts clock cycles to define the pulse width and period.

• reg pulse;: holds the pulse signal (1 or 0).
• always @(posedge clk): triggers on clock rising edge.
• counter: counts clock cycles to control pulse timing.

verilog

module pulse_generator(
    input wire clk,
    input wire reset,
    output reg pulse
);

    reg [4:0] counter;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            counter <= 0;
            pulse <= 0;
        end else begin
            if (counter < 5'd10) begin
                pulse <= 1;
                counter <= counter + 1;
            end else if (counter < 5'd20) begin
                pulse <= 0;
                counter <= counter + 1;
            end else begin
                counter <= 0;
            end
        end
    end

endmodule

Example

This example creates a pulse that stays high for 10 clock cycles and low for the next 10, repeating continuously. The pulse output toggles accordingly, simulating a pulse generator.

verilog

module pulse_generator(
    input wire clk,
    input wire reset,
    output reg pulse
);

    reg [4:0] counter;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            counter <= 0;
            pulse <= 0;
        end else begin
            if (counter < 5'd10) begin
                pulse <= 1;
                counter <= counter + 1;
            end else if (counter < 5'd20) begin
                pulse <= 0;
                counter <= counter + 1;
            end else begin
                counter <= 0;
            end
        end
    end

endmodule

Output

At each clock cycle, pulse is 1 for 10 cycles, then 0 for 10 cycles, repeating.

Common Pitfalls

Common mistakes when writing a pulse generator include:

• Not resetting the counter properly, causing the pulse timing to drift.
• Using blocking assignments (=) inside always @(posedge clk) blocks instead of non-blocking (<=), which can cause simulation mismatches.
• Not handling asynchronous reset correctly, leading to unpredictable pulse start.

verilog

/* Wrong: Using blocking assignment and missing reset */
module wrong_pulse(
    input wire clk,
    output reg pulse
);
    reg [4:0] counter;
    always @(posedge clk) begin
        if (counter < 10) begin
            pulse = 1; // blocking assignment - wrong
            counter = counter + 1;
        end else if (counter < 20) begin
            pulse = 0;
            counter = counter + 1;
        end else begin
            counter = 0;
        end
    end
endmodule

/* Correct: Using non-blocking assignment and reset */
module correct_pulse(
    input wire clk,
    input wire reset,
    output reg pulse
);
    reg [4:0] counter;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            counter <= 0;
            pulse <= 0;
        end else begin
            if (counter < 10) begin
                pulse <= 1;
                counter <= counter + 1;
            end else if (counter < 20) begin
                pulse <= 0;
                counter <= counter + 1;
            end else begin
                counter <= 0;
            end
        end
    end
endmodule

Quick Reference

Tips for writing pulse generators in Verilog:

• Use reg for signals that change inside always blocks.
• Use non-blocking assignments (<=) inside clocked always blocks.
• Include asynchronous reset to initialize counters and outputs.
• Control pulse width by counting clock cycles.
• Test your design with a testbench to verify timing.

Key Takeaways

Use a counter inside an always block triggered by clock edges to control pulse timing.

Always use non-blocking assignments (<=) in clocked always blocks for correct simulation.

Include a reset signal to initialize the pulse and counter reliably.

Pulse width is controlled by how long the pulse signal stays high in clock cycles.

Test your pulse generator with a testbench to ensure correct timing behavior.