How to Connect Modules in Verilog: Syntax and Examples

In Verilog, you connect modules by instantiating one module inside another using the module_name instance_name (port_connections); syntax. Ports are connected by name or position to link signals between modules.

Syntax

To connect modules in Verilog, you use module instantiation. This means creating an instance of one module inside another and connecting their ports.

The general syntax is:

module_name instance_name (port_connections);

Here:

• module_name is the name of the module you want to use.
• instance_name is a unique name for this instance.
• port_connections connects the instance ports to signals in the parent module, either by position or by name.

verilog

module_name instance_name (port1, port2, ...);

// Or using named connections:
module_name instance_name (
  .port1(signal1),
  .port2(signal2),
  ...
);

Example

This example shows how to connect a simple and_gate module inside a top_module. The and_gate has two inputs and one output.

The top_module creates signals and connects them to the and_gate instance using named port connections.

verilog

module and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

module top_module();
  wire x, z, w;
  assign x = 1'b1;
  assign z = 1'b0;

  and_gate u1 (.a(x), .b(z), .y(w));

  initial begin
    $display("Output w = %b", w);
  end
endmodule

Output

Output w = 0

Common Pitfalls

• Port order mismatch: Connecting ports by position can cause errors if the order is wrong. Use named connections to avoid this.
• Missing signals: Forgetting to declare wires or regs for connections leads to errors.
• Wrong port directions: Inputs and outputs must match the module definition.

verilog

/* Wrong: positional connection with wrong order */
// and_gate u1 (w, x, z); // Incorrect port order

/* Right: named connections avoid order mistakes */
and_gate u1 (.a(x), .b(z), .y(w));

Quick Reference

Remember these tips when connecting modules:

• Use module_name instance_name (port_connections); to instantiate.
• Prefer named port connections .port(signal) for clarity.
• Declare all connecting signals (wire/reg) in the parent module.
• Match port directions and widths exactly.

Key Takeaways

Connect modules by instantiating one inside another using the module name and instance name.

Use named port connections to avoid errors from port order mismatches.

Declare all signals connecting modules properly as wires or regs.

Ensure port directions and widths match between connected modules.

Test connections with simple examples and $display to verify outputs.