Verilog Code for T Flip Flop: Syntax and Example

A T flip flop in Verilog toggles its output on every clock pulse when the input T is high. The basic code uses an always block triggered on the clock's rising edge, toggling the output if T is 1.

Syntax

The basic syntax for a T flip flop in Verilog uses an always block sensitive to the clock's rising edge. Inside, it checks if the input T is high (1). If yes, it toggles the output Q; otherwise, Q remains the same.

• input clk: Clock signal triggering the flip flop.
• input T: Toggle input; when 1, output toggles.
• output reg Q: Output storing the flip flop state.

verilog

always @(posedge clk) begin
    if (T) begin
        Q <= ~Q; // Toggle output
    end
end

Example

This example shows a complete T flip flop module with asynchronous reset. When reset is high, output Q resets to 0. On each rising clock edge, if T is 1, Q toggles; if T is 0, Q holds its value.

verilog

module t_flip_flop(
    input clk,
    input reset,
    input T,
    output reg Q
);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        Q <= 1'b0; // Reset output to 0
    end else if (T) begin
        Q <= ~Q; // Toggle output
    end
end

endmodule

Common Pitfalls

Common mistakes when coding a T flip flop include:

• Forgetting to use non-blocking assignment <= inside always blocks, which can cause simulation mismatches.
• Not including a reset signal, which can leave the output in an unknown state at startup.
• Using blocking assignment = inside sequential logic, which is incorrect.
• Missing the clock edge sensitivity, causing combinational instead of sequential behavior.

verilog

/* Wrong way: blocking assignment and missing reset */
always @(posedge clk) begin
    if (T) begin
        Q = ~Q; // Wrong: blocking assignment
    end
end

/* Right way: non-blocking assignment with reset */
always @(posedge clk or posedge reset) begin
    if (reset) begin
        Q <= 1'b0;
    end else if (T) begin
        Q <= ~Q;
    end
end

Quick Reference

Signal	Description
clk	Clock input triggering flip flop on rising edge
reset	Asynchronous reset to set output Q to 0
T	Toggle input; when 1, output Q toggles
Q	Output storing current state of flip flop

Key Takeaways

Use an always block triggered on the clock's rising edge to model T flip flop behavior.

Toggle output Q only when input T is high using non-blocking assignment <=.

Include an asynchronous reset to initialize output Q safely.

Avoid blocking assignments (=) inside sequential always blocks.

Ensure sensitivity list includes clock edge and reset signals if used.