How to Simulate Verilog on FPGA: Step-by-Step Guide

To simulate Verilog on an FPGA, first write a testbench that applies inputs and checks outputs of your design. Then use a simulation tool like ModelSim or Vivado Simulator to run the testbench and verify behavior before programming the FPGA.

Syntax

A Verilog simulation involves two main parts: the design module and the testbench module. The design module contains your hardware logic. The testbench module applies inputs and observes outputs without any ports.

• module design_name(...); - Your hardware design.
• module testbench_name(); - Testbench with no ports.
• initial begin ... end - Block to apply stimulus once at simulation start.
• always - Block to create repeating signals like clocks.

verilog

module design(input wire a, b, output wire y);
  assign y = a & b;
endmodule

module testbench();
  reg a, b;
  wire y;

  design uut(.a(a), .b(b), .y(y));

  initial begin
    a = 0; b = 0;
    #10 a = 1; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Example

This example shows a simple AND gate design and a testbench that simulates all input combinations. The simulation tool will show how output y changes with inputs a and b.

verilog

module and_gate(input wire a, b, output wire y);
  assign y = a & b;
endmodule

module testbench();
  reg a, b;
  wire y;

  and_gate uut(.a(a), .b(b), .y(y));

  initial begin
    $monitor("At time %0t: a=%b b=%b y=%b", $time, a, b, y);
    a = 0; b = 0;
    #10 a = 1; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Output

At time 0: a=0 b=0 y=0
At time 10: a=1 b=0 y=0
At time 20: a=0 b=1 y=0
At time 30: a=1 b=1 y=1

Common Pitfalls

Common mistakes when simulating Verilog for FPGA include:

• Not writing a testbench, so no inputs are applied.
• Forgetting to use $finish to end simulation, causing it to run forever.
• Using blocking assignments (=) incorrectly in sequential logic.
• Not initializing signals, leading to unknown values (x or z).

Always verify your testbench applies all needed inputs and ends cleanly.

verilog

/* Wrong: No $finish, simulation runs forever */
module testbench();
  reg a, b;
  initial begin
    a = 0; b = 0;
    #10 a = 1; b = 1;
  end
endmodule

/* Right: Ends simulation properly */
module testbench();
  reg a, b;
  initial begin
    a = 0; b = 0;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Quick Reference

Steps to simulate Verilog on FPGA:

• Write your design module.
• Create a testbench module with stimulus.
• Use a simulator (ModelSim, Vivado) to run the testbench.
• Check waveforms or console output for correctness.
• Fix bugs and repeat until design works as expected.

Key Takeaways

Write a testbench to apply inputs and check outputs before FPGA programming.

Use simulation tools like ModelSim or Vivado Simulator to run your testbench.

Always include $finish in your testbench to stop simulation cleanly.

Initialize all signals to avoid unknown values during simulation.

Check simulation output carefully to verify your design logic.