VerilogHow-ToBeginner · 3 min read

How to Use $finish and $stop in Verilog: Syntax and Examples

In Verilog, $finish ends the entire simulation and closes it, while $stop pauses the simulation and enters interactive debug mode. Use $finish when you want to completely end simulation, and $stop when you want to halt temporarily for inspection.

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Syntax

The $finish and $stop system tasks are used to control simulation flow in Verilog.

$finish; - Ends the simulation and exits.
$stop; - Pauses the simulation and waits for user interaction or debugger.

Both are called as tasks with a semicolon and do not take arguments.

verilog

$finish;
$stop;

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Example

This example shows a simple testbench that uses $stop to pause simulation and $finish to end it after a few clock cycles.

verilog

module testbench();
  reg clk = 0;
  integer count = 0;

  always #5 clk = ~clk; // Clock toggles every 5 time units

  initial begin
    $display("Simulation started");
    forever begin
      @(posedge clk);
      count = count + 1;
      $display("Clock cycle: %0d", count);
      if (count == 3) begin
        $stop; // Pause simulation here
      end
      if (count == 5) begin
        $finish; // End simulation here
      end
    end
  end
endmodule

Output

Simulation started Clock cycle: 1 Clock cycle: 2 Clock cycle: 3 // Simulation pauses here (user must resume) Clock cycle: 4 Clock cycle: 5 // Simulation ends here

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Common Pitfalls

Common mistakes when using $finish and $stop include:

Using $stop expecting simulation to end; it only pauses.
Placing $finish too early, causing simulation to exit before important checks.
Not resuming simulation after $stop, which can make it seem like simulation is stuck.

Always plan where to pause or end simulation carefully.

verilog

/* Wrong: Using $stop expecting simulation to end */
initial begin
  $stop; // Simulation pauses but does not exit
  $display("This line still runs after resume");
end

/* Right: Use $finish to end simulation */
initial begin
  $finish; // Simulation ends immediately
  $display("This line will NOT run");
end

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Quick Reference

System Task	Effect	Typical Use
$finish	Ends simulation and exits	Use to stop simulation completely when done
$stop	Pauses simulation, enters debug mode	Use to pause and inspect signals during simulation

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Key Takeaways

Use $finish to completely end a Verilog simulation.

Use $stop to pause simulation and allow debugging or inspection.

$stop does not end simulation; it only halts it temporarily.

Place $finish and $stop carefully to control simulation flow.

After $stop, simulation must be resumed manually to continue.