How to Declare Vector in Verilog: Syntax and Examples

In Verilog, you declare a vector by specifying the bit width in square brackets before the variable name, like reg [7:0] my_vector;. This creates an 8-bit vector where bits are indexed from 7 down to 0.

Syntax

To declare a vector in Verilog, use the format type [msb:lsb] name; where:

• type is usually reg or wire.
• msb is the most significant bit index (highest number).
• lsb is the least significant bit index (lowest number).
• name is the variable identifier.

The range [msb:lsb] defines the vector width and bit order.

verilog

reg [7:0] my_vector; // 8-bit vector from bit 7 down to bit 0
wire [15:0] data_bus; // 16-bit vector from bit 15 down to bit 0

Example

This example shows how to declare an 8-bit register vector and assign a value to it inside an initial block.

verilog

module vector_example();
  reg [7:0] my_vector;

  initial begin
    my_vector = 8'b10101010; // Assign binary value to vector
    $display("my_vector = %b", my_vector); // Print the vector value
  end
endmodule

Output

my_vector = 10101010

Common Pitfalls

Common mistakes when declaring vectors include:

• Forgetting to specify the bit range, which defaults to 1-bit scalar.
• Using [lsb:msb] instead of [msb:lsb], which can cause confusion or errors.
• Mixing wire and reg types incorrectly for vectors.

Always ensure the bit range is correct and matches your design intent.

verilog

/* Wrong: no range specified, creates 1-bit scalar */
reg my_vector_wrong;

/* Correct: specify range for 8-bit vector */
reg [7:0] my_vector_right;

Quick Reference

Declaration Part	Description	Example
type	Data type (reg or wire)	reg, wire
[msb:lsb]	Bit range for vector width	[7:0], [15:0]
name	Variable identifier	my_vector, data_bus
Example	Full declaration	reg [7:0] my_vector;

Key Takeaways

Declare vectors by specifying bit width in square brackets before the variable name.

Use [msb:lsb] format to define vector size and bit order.

Choose reg or wire type based on usage context.

Always specify the bit range to avoid default 1-bit scalar.

Check bit order to match your design requirements.