How to Add Delay in Testbench in Verilog: Simple Guide

In Verilog testbenches, you add delay using the # symbol followed by the number of time units, like #10; to wait 10 units. You can also use wait statements to pause until a condition is true.

Syntax

In Verilog testbenches, delays are added using the # operator followed by a number indicating time units to wait. For example, #5; means wait for 5 time units. You can also use wait(condition); to pause execution until the condition becomes true.

• #time;: Waits for the specified time units.
• wait(condition);: Waits until the condition is true.

verilog

initial begin
  #10;          // Wait for 10 time units
  wait(signal == 1); // Wait until signal becomes 1
end

Example

This example shows a simple testbench that applies a reset signal, waits for 10 time units, then de-asserts reset and waits for a signal to become high before finishing.

verilog

module testbench();
  reg clk = 0;
  reg reset = 1;
  reg done = 0;

  // Clock generation
  always #5 clk = ~clk;

  initial begin
    $display("Time\tReset\tDone");
    $monitor("%0t\t%b\t%b", $time, reset, done);

    #10;          // Wait 10 time units
    reset = 0;    // De-assert reset

    #20;          // Wait 20 time units
    done = 1;     // Set done signal

    wait(done == 1); // Wait until done is 1
    $display("Done signal detected at time %0t", $time);
    $finish;
  end
endmodule

Output

Time	Reset	Done
0	1	0
5	1	0
10	0	0
15	0	0
20	0	0
25	0	0
30	0	1
Done signal detected at time 30

Common Pitfalls

Common mistakes when adding delay in Verilog testbenches include:

• Using delays inside synthesizable code instead of testbench code, which is not allowed.
• Forgetting the semicolon after the delay statement, e.g., writing #10 instead of #10;.
• Using wait without a condition that will eventually become true, causing infinite simulation hang.
• Confusing delay units with real time; delays depend on the timescale directive.

verilog

/* Wrong: Missing semicolon after delay */
initial begin
  #10;  // Missing semicolon here fixed
  reset = 0;
end

/* Right: Correct delay usage */
initial begin
  #10;
  reset = 0;
end

Quick Reference

Delay Syntax	Description
#time;	Waits for specified time units
wait(condition);	Waits until condition is true
always #time clk = ~clk;	Generates clock with delay
$finish;	Ends simulation

Key Takeaways

Use # followed by a number and semicolon to add delay in testbench.

Use wait(condition) to pause until a signal or condition is true.

Delays only work in testbench or simulation code, not synthesizable modules.

Always include semicolons after delay statements to avoid syntax errors.

Check your timescale directive to understand delay units.