Verilog Code for Sequence Detector 1010: Syntax and Example

A sequence detector 1010 in Verilog can be implemented using a finite state machine that tracks input bits and detects the pattern 1010. The code uses states to remember progress and outputs a signal when the sequence is found.

Syntax

The sequence detector uses a module with inputs for clock and data, and an output to signal detection. It defines states using parameter and uses a case statement inside an always @(posedge clk) block to update states and output.

• module: Defines the hardware block.
• input clk, data: Clock and serial input bit.
• output reg detected: Output high when sequence 1010 is detected.
• state: Holds current FSM state.
• always @(posedge clk): Updates state on clock rising edge.
• case: Controls state transitions based on input.

verilog

module seq_detector_1010(
    input clk,
    input data,
    output reg detected
);

    // Define states
    parameter S0 = 3'b000, // Initial state
              S1 = 3'b001, // Detected '1'
              S2 = 3'b010, // Detected '10'
              S3 = 3'b011, // Detected '101'
              S4 = 3'b100; // Detected '1010' (output state)

    reg [2:0] state, next_state;

    // State register update
    always @(posedge clk) begin
        state <= next_state;
    end

    // Next state logic and output
    always @(*) begin
        detected = 0;
        case(state)
            S0: next_state = data ? S1 : S0;
            S1: next_state = data ? S1 : S2;
            S2: next_state = data ? S3 : S0;
            S3: begin
                if (data) begin
                    next_state = S1;
                    detected = 0;
                end else begin
                    next_state = S4;
                    detected = 1;
                end
            end
            S4: begin
                detected = 1;
                next_state = data ? S1 : S2;
            end
            default: next_state = S0;
        endcase
    end

endmodule

Example

This example shows a complete Verilog module for a 1010 sequence detector using a finite state machine. It outputs detected = 1 when the input sequence 1010 is found on the data input synchronized to the clk.

verilog

module testbench;
    reg clk = 0;
    reg data = 0;
    wire detected;

    seq_detector_1010 uut(
        .clk(clk),
        .data(data),
        .detected(detected)
    );

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        // Test input sequence: 1 0 1 0 1 0
        data = 0; #10;
        data = 1; #10;
        data = 0; #10;
        data = 1; #10;
        data = 0; #10;
        data = 1; #10;
        data = 0; #10;
        data = 0; #10;
        $finish;
    end

    initial begin
        $monitor("At time %0t: data=%b detected=%b", $time, data, detected);
    end
endmodule

Output

At time 10: data=1 detected=0
At time 20: data=0 detected=0
At time 30: data=1 detected=0
At time 40: data=0 detected=1
At time 50: data=1 detected=0
At time 60: data=0 detected=1
At time 70: data=0 detected=0
At time 80: data=0 detected=0

Common Pitfalls

Common mistakes when coding a sequence detector include:

• Not resetting the state machine properly, causing incorrect detection.
• Failing to handle overlapping sequences, which can miss detections.
• Incorrect state transitions that do not reflect the sequence logic.
• Assigning output signals inside the clocked block incorrectly, causing glitches.

Always use non-blocking assignments (<=) for state updates and combinational logic for next state and output.

verilog

/* Wrong: Using blocking assignment for state update */
always @(posedge clk) begin
    state = next_state; // Wrong: should be <=
end

/* Right: Using non-blocking assignment */
always @(posedge clk) begin
    state <= next_state; // Correct
end

Quick Reference

• States: Use parameters to name states clearly.
• State register: Update state on clock edge with non-blocking assignment.
• Next state logic: Use combinational always @(*) block with case statement.
• Output: Assign output signals in combinational block based on current state and input.
• Overlapping sequences: Design states to allow detection of sequences that share bits.

Key Takeaways

Use a finite state machine with clearly defined states to detect the 1010 sequence.

Update states on the clock's rising edge using non-blocking assignments.

Design next state logic combinationally with a case statement for clarity.

Handle overlapping sequences by proper state transitions to avoid missed detections.

Assign output signals in combinational logic to prevent glitches.