Verilog Code for 4 Bit Adder: Syntax and Example

A 4 bit adder in Verilog adds two 4-bit inputs and produces a 4-bit sum and a carry out. Use module to define inputs, outputs, and the addition logic with the assign statement or by instantiating full adders.

Syntax

The basic syntax for a 4 bit adder module includes declaring inputs and outputs, then defining the addition logic. Inputs are two 4-bit vectors and an optional carry-in. Outputs are a 4-bit sum and a carry-out bit.

• module: starts the module definition
• input [3:0]: 4-bit input vectors
• output [3:0]: 4-bit sum output
• output carry_out: carry output bit
• assign: continuous assignment for combinational logic

verilog

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum,
    output carry_out
);

assign {carry_out, sum} = a + b;

endmodule

Example

This example shows a complete 4 bit adder module that adds two 4-bit numbers and outputs the sum and carry out. It uses the assign statement to perform addition directly.

verilog

module four_bit_adder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum,
    output carry_out
);

assign {carry_out, sum} = a + b;

endmodule

// Testbench to verify the 4 bit adder
module testbench();
    reg [3:0] a, b;
    wire [3:0] sum;
    wire carry_out;

    four_bit_adder uut(.a(a), .b(b), .sum(sum), .carry_out(carry_out));

    initial begin
        a = 4'b0011; b = 4'b0101; // 3 + 5
        #10;
        $display("a=%b b=%b sum=%b carry_out=%b", a, b, sum, carry_out);

        a = 4'b1111; b = 4'b0001; // 15 + 1
        #10;
        $display("a=%b b=%b sum=%b carry_out=%b", a, b, sum, carry_out);

        a = 4'b1010; b = 4'b0101; // 10 + 5
        #10;
        $display("a=%b b=%b sum=%b carry_out=%b", a, b, sum, carry_out);

        $finish;
    end
endmodule

Output

a=0011 b=0101 sum=1000 carry_out=0
a=1111 b=0001 sum=0000 carry_out=1
a=1010 b=0101 sum=1111 carry_out=0

Common Pitfalls

Common mistakes when writing a 4 bit adder in Verilog include:

• Not using the correct bit width for inputs and outputs, causing truncation or overflow.
• Forgetting to include the carry out bit in the output, which is important for multi-bit addition.
• Using blocking assignments (=) inside combinational logic instead of continuous assignments (assign).
• Not testing edge cases like maximum values (e.g., 15 + 1) which cause carry out.

verilog

/* Wrong: Missing carry_out and wrong assignment */
module wrong_adder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum
);

// This will ignore carry out and may cause incorrect sum
assign sum = a + b;

endmodule

/* Right: Include carry_out and use concatenation */
module correct_adder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum,
    output carry_out
);

assign {carry_out, sum} = a + b;

endmodule

Quick Reference

Summary tips for writing a 4 bit adder in Verilog:

• Use input [3:0] and output [3:0] for 4-bit buses.
• Use assign {carry_out, sum} = a + b; to get sum and carry out.
• Test with edge cases like maximum inputs to verify carry out.
• Use a testbench to simulate and verify your design.

Key Takeaways

Define inputs and outputs with correct 4-bit widths and include carry out.

Use continuous assignment with concatenation to get sum and carry out in one step.

Always test your adder with edge cases to ensure correct carry behavior.

Avoid blocking assignments for combinational logic; use assign statements.

A testbench helps verify your 4 bit adder works as expected.