Verilog Code for Half Adder: Syntax and Example

A half adder in Verilog uses assign statements to compute the sum and carry outputs from two input bits. The sum is the XOR of the inputs, and the carry is the AND of the inputs, implemented as assign sum = a ^ b; and assign carry = a & b;.

Syntax

A half adder module in Verilog has two inputs and two outputs. The inputs are the bits to add, and the outputs are the sum and carry bits. The assign keyword is used to define combinational logic for sum and carry.

• module: Defines the module name and ports.
• input: Declares input signals.
• output: Declares output signals.
• assign: Creates continuous assignments for outputs.

verilog

module half_adder(
    input a,
    input b,
    output sum,
    output carry
);

assign sum = a ^ b;      // XOR for sum
assign carry = a & b;    // AND for carry

endmodule

Example

This example shows a complete half adder module and a testbench that applies all input combinations. It demonstrates how the sum and carry outputs change based on inputs a and b.

verilog

module half_adder(
    input a,
    input b,
    output sum,
    output carry
);

assign sum = a ^ b;
assign carry = a & b;

endmodule

module testbench;
    reg a, b;
    wire sum, carry;

    half_adder ha(.a(a), .b(b), .sum(sum), .carry(carry));

    initial begin
        $display("a b | sum carry");
        a = 0; b = 0; #10 $display("%b %b |  %b    %b", a, b, sum, carry);
        a = 0; b = 1; #10 $display("%b %b |  %b    %b", a, b, sum, carry);
        a = 1; b = 0; #10 $display("%b %b |  %b    %b", a, b, sum, carry);
        a = 1; b = 1; #10 $display("%b %b |  %b    %b", a, b, sum, carry);
        $finish;
    end
endmodule

Output

a b | sum carry
0 0 |  0    0
0 1 |  1    0
1 0 |  1    0
1 1 |  0    1

Common Pitfalls

Common mistakes when writing a half adder in Verilog include:

• Using = instead of assign for combinational logic outside procedural blocks.
• Mixing up the sum and carry logic formulas.
• Forgetting to declare inputs and outputs correctly.

Always use assign for continuous assignments and verify the logic expressions.

verilog

/* Wrong way: Using procedural assignment without always block */
module wrong_half_adder(
    input a,
    input b,
    output sum,
    output carry
);

assign sum = a ^ b;    // Error fixed: use assign for continuous assignment
assign carry = a & b;  // Error fixed

endmodule

/* Correct way: Use assign for combinational logic */
module correct_half_adder(
    input a,
    input b,
    output sum,
    output carry
);

assign sum = a ^ b;
assign carry = a & b;

endmodule

Quick Reference

Component	Description	Verilog Syntax
Module	Defines the half adder block	module half_adder(input a, input b, output sum, output carry); ... endmodule
Input	Bits to add	input a, b;
Output	Sum and carry bits	output sum, carry;
Sum Logic	XOR of inputs	assign sum = a ^ b;
Carry Logic	AND of inputs	assign carry = a & b;

Key Takeaways

Use assign statements for combinational logic in a half adder.

Sum is the XOR of inputs; carry is the AND of inputs.

Always declare inputs and outputs clearly in the module header.

Avoid procedural assignments without always blocks for simple combinational logic.

Test all input combinations to verify correct half adder behavior.