What is always_comb in SystemVerilog: Explanation and Example

always_comb is a SystemVerilog procedural block that automatically infers combinational logic without needing manual sensitivity lists. It ensures the block runs whenever any input changes, making your code safer and easier to write compared to traditional always @(*) blocks.

How It Works

Think of always_comb as a smart assistant that watches all the inputs you use inside its block. Whenever any input changes, it automatically runs the block to update the outputs. This means you don't have to list which signals to watch, unlike older Verilog where you manually specify sensitivity lists.

This automatic watching helps prevent mistakes where you forget to include a signal, which can cause bugs. It also clearly tells the compiler and other engineers that this block is purely combinational logic, like a calculator that instantly updates its answer when you change the numbers.

Example

This example shows a simple combinational logic block using always_comb to assign the output as the AND of two inputs.

systemverilog

module comb_example(input logic a, input logic b, output logic y);
  always_comb begin
    y = a & b;
  end
endmodule

When to Use

Use always_comb whenever you want to describe combinational logic in SystemVerilog. It is perfect for logic that depends only on current inputs and has no memory or clock.

For example, use it for multiplexers, simple arithmetic, or logic gates. It helps avoid bugs from incomplete sensitivity lists and makes your code easier to read and maintain.

Key Points

• always_comb automatically infers sensitivity lists.
• It is used for combinational logic only.
• Helps prevent bugs from missing signals in sensitivity lists.
• Improves code clarity and maintenance.
• Replaces older always @(*) blocks in SystemVerilog.

Key Takeaways

always_comb runs whenever any input changes, ensuring correct combinational logic.

It removes the need to manually specify sensitivity lists, reducing errors.

Use it for all combinational logic blocks in SystemVerilog for clearer, safer code.

It replaces the older always @(*) style with better semantics.