How to Create Hierarchical Design in Verilog: Syntax and Example

In Verilog, hierarchical design is created by defining multiple module blocks and connecting them using module instantiation. You instantiate a lower-level module inside a higher-level module by declaring its name and wiring its ports, enabling modular and reusable designs.

Syntax

Hierarchical design in Verilog uses module instantiation to connect smaller modules inside bigger ones. The syntax includes:

• module_name instance_name (port_connections); - to create an instance of a module.
• Port connections can be by position or by name.
• Each module defines inputs, outputs, and internal logic.

verilog

module child_module(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

module parent_module(input wire x1, input wire x2, output wire z);
  child_module u1(.a(x1), .b(x2), .y(z));
endmodule

Example

This example shows a simple AND gate module child_module instantiated inside a parent_module. The parent module connects its inputs to the child and outputs the result.

verilog

module child_module(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

module parent_module(input wire x1, input wire x2, output wire z);
  child_module u1(.a(x1), .b(x2), .y(z));
endmodule

// Testbench to simulate the design
module testbench();
  reg x1, x2;
  wire z;

  parent_module uut(.x1(x1), .x2(x2), .z(z));

  initial begin
    $monitor("x1=%b x2=%b z=%b", x1, x2, z);
    x1 = 0; x2 = 0; #10;
    x1 = 0; x2 = 1; #10;
    x1 = 1; x2 = 0; #10;
    x1 = 1; x2 = 1; #10;
    $finish;
  end
endmodule

Output

x1=0 x2=0 z=0
x1=0 x2=1 z=0
x1=1 x2=0 z=0
x1=1 x2=1 z=1

Common Pitfalls

Common mistakes when creating hierarchical designs include:

• Not matching port names or widths between modules.
• Forgetting to instantiate the child module inside the parent.
• Using positional port connections incorrectly, causing wrong wiring.
• Not declaring signals properly in the parent module to connect to child ports.

Always use named port connections for clarity and fewer errors.

verilog

/* Wrong: positional connection mismatch */
module parent_wrong(input wire x1, input wire x2, output wire z);
  child_module u1(x1, z, x2); // ports mixed up
endmodule

/* Correct: named port connection */
module parent_correct(input wire x1, input wire x2, output wire z);
  child_module u1(.a(x1), .b(x2), .y(z));
endmodule

Quick Reference

Tips for hierarchical design in Verilog:

• Define small, reusable modules.
• Instantiate modules inside higher-level modules using named port mapping.
• Keep port names consistent for easy wiring.
• Use testbenches to verify each module and the full hierarchy.

Key Takeaways

Hierarchical design in Verilog is done by instantiating modules inside other modules.

Use named port connections to avoid wiring mistakes and improve readability.

Always match port widths and names between parent and child modules.

Test each module separately and then test the full hierarchy with a testbench.

Clear module boundaries make your design modular and easier to maintain.