How to Write Asynchronous Reset in Verilog: Syntax and Example

In Verilog, an asynchronous reset is written inside an always block triggered by the clock and reset signals. Use posedge reset or negedge reset in the sensitivity list to immediately reset the register regardless of the clock.

Syntax

The asynchronous reset is implemented in an always block with both clock and reset in the sensitivity list. The reset condition is checked first to immediately set the register to a known state. The clock edge triggers normal operation when reset is inactive.

• posedge clk: triggers on the rising edge of the clock.
• posedge reset or negedge reset: triggers on reset signal change to asynchronously reset.
• Inside the block, if (reset) sets registers to initial values immediately.

verilog

always @(posedge clk or posedge reset) begin
  if (reset) begin
    // reset logic
  end else begin
    // normal operation
  end
end

Example

This example shows a simple 4-bit counter with asynchronous active-high reset. When reset is high, the counter resets to zero immediately, ignoring the clock. When reset is low, the counter increments on each clock rising edge.

verilog

module async_reset_counter(
  input wire clk,
  input wire reset,
  output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 4'b0000; // asynchronous reset
  end else begin
    count <= count + 1; // normal counting
  end
end

endmodule

Common Pitfalls

Common mistakes when writing asynchronous reset include:

• Forgetting to include reset in the sensitivity list, causing reset to behave synchronously.
• Using synchronous reset style but naming it asynchronous, leading to confusion.
• Not properly initializing registers on reset, causing unknown states.
• Using active-low reset but coding active-high logic or vice versa.

Always verify the reset polarity and sensitivity list match your design requirements.

verilog

/* Wrong: reset missing in sensitivity list (synchronous reset) */
always @(posedge clk) begin
  if (reset) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

/* Right: reset included for asynchronous reset */
always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 0;
  end else begin
    count <= count + 1;
  end
end

Quick Reference

Tips for writing asynchronous reset in Verilog:

• Include reset signal in the always block sensitivity list with the clock.
• Check reset condition first inside the block to immediately reset registers.
• Use posedge or negedge for reset depending on active-high or active-low design.
• Initialize all registers on reset to avoid unknown states.

Key Takeaways

Always include the reset signal in the sensitivity list for asynchronous reset.

Check the reset condition first inside the always block to reset immediately.

Match reset polarity (active-high or active-low) with your design requirements.

Initialize all registers during reset to avoid unknown states.

Avoid confusing synchronous reset with asynchronous by proper sensitivity list usage.