Verilog Code for D Latch: Syntax, Example, and Tips

A D latch in Verilog can be coded using an always block sensitive to the enable signal and data input. The latch stores the input D when the enable EN is high and holds the value when EN is low.

Syntax

The basic syntax for a D latch in Verilog uses an always block triggered by changes in the enable signal or data input. Inside, an if statement checks if the enable is high to update the output Q with the input D. Otherwise, Q keeps its previous value.

• module: Defines the latch module.
• input D: Data input to be latched.
• input EN: Enable signal controlling when data is latched.
• output reg Q: Output storing the latched value.
• always @ (EN or D): Sensitivity list triggers on changes to EN or D.
• if (EN): When enable is high, latch updates Q.

verilog

module d_latch (input D, input EN, output reg Q);
  always @ (EN or D) begin
    if (EN)
      Q = D;
  end
endmodule

Example

This example shows a D latch module and a testbench that applies different inputs to demonstrate how the latch stores data when enabled and holds it when disabled.

verilog

module d_latch (input D, input EN, output reg Q);
  always @ (EN or D) begin
    if (EN)
      Q = D;
  end
endmodule

module testbench;
  reg D, EN;
  wire Q;

  d_latch uut (.D(D), .EN(EN), .Q(Q));

  initial begin
    $monitor("Time=%0t EN=%b D=%b Q=%b", $time, EN, D, Q);
    EN = 0; D = 0;
    #5 D = 1;
    #5 EN = 1;
    #5 D = 0;
    #5 EN = 0;
    #5 D = 1;
    #5 $finish;
  end
endmodule

Output

Time=0 EN=0 D=0 Q=x
Time=5 EN=0 D=1 Q=x
Time=10 EN=1 D=1 Q=1
Time=15 EN=1 D=0 Q=0
Time=20 EN=0 D=0 Q=0
Time=25 EN=0 D=1 Q=0

Common Pitfalls

Common mistakes when coding a D latch include:

• Not including both EN and D in the sensitivity list, causing simulation mismatches.
• Using non-blocking assignments (<=) inside the latch, which is meant for sequential logic, not level-sensitive latches.
• Forgetting to declare Q as reg, which is required for variables assigned inside always blocks.

verilog

/* Wrong: Missing D in sensitivity list and using non-blocking assignment */
module wrong_latch(input D, input EN, output reg Q);
  always @ (EN) begin
    if (EN)
      Q <= D; // non-blocking used incorrectly
  end
endmodule

/* Corrected version */
module correct_latch(input D, input EN, output reg Q);
  always @ (EN or D) begin
    if (EN)
      Q = D; // blocking assignment for latch
  end
endmodule

Quick Reference

D Latch Quick Tips:

• Use always @ (EN or D) for sensitivity.
• Use blocking assignment = inside the latch.
• Declare output as reg.
• Latch updates output only when EN is high.
• When EN is low, output holds previous value.

Key Takeaways

A D latch stores input data when enable is high and holds it when enable is low.

Use an always block sensitive to both enable and data signals for correct behavior.

Use blocking assignments (=) inside the latch, not non-blocking (<=).

Declare the output as reg to allow assignment inside always blocks.

Include all relevant signals in the sensitivity list to avoid simulation mismatches.