How to Model Decoder Using Assign in Verilog

In Verilog, you can model a decoder using the assign statement by creating combinational logic that maps input bits to output lines. Typically, a decoder with n inputs and 2^n outputs is implemented by assigning each output line a condition that matches one input combination using equality comparison.

Syntax

The basic syntax to model a decoder using assign in Verilog is:

• assign output_line = (input == value); where output_line is one bit of the output and input is the input vector.
• Each output line corresponds to one unique input pattern.
• Use equality comparison to check if input matches the pattern.

verilog

assign out[0] = (in == 2'b00);
assign out[1] = (in == 2'b01);
assign out[2] = (in == 2'b10);
assign out[3] = (in == 2'b11);

Example

This example shows a 2-to-4 decoder modeled using assign. The 2-bit input in selects one of the 4 output lines to be high (1), others low (0).

verilog

module decoder_2to4(
    input [1:0] in,
    output wire [3:0] out
);

assign out[0] = (in == 2'b00);
assign out[1] = (in == 2'b01);
assign out[2] = (in == 2'b10);
assign out[3] = (in == 2'b11);

endmodule

Common Pitfalls

Common mistakes when modeling decoders with assign include:

• Not using equality comparison == and instead using assignment = inside assign.
• Forgetting that outputs must be one-hot encoded (only one output high at a time).
• Not declaring outputs as wires when using assign.
• Using blocking assignments = inside assign which is illegal; assign uses continuous assignment.

Wrong:

assign out[0] = in = 2'b00; // incorrect use of =

Right:

assign out[0] = (in == 2'b00);

verilog

/* Wrong way */
// assign out[0] = in = 2'b00; // Syntax error

/* Right way */
assign out[0] = (in == 2'b00);

Quick Reference

Concept	Description
assign	Used for continuous assignment of combinational logic
Decoder input	Binary vector selecting output line
Output lines	One-hot encoded outputs, each assigned a condition
Equality check	Use '==' to compare input with constant
Output type	Declare outputs as wire for assign statements

Key Takeaways

Use continuous assign statements with equality checks to model decoder outputs.

Each output line corresponds to one unique input pattern and is one-hot encoded.

Always declare outputs as wires when using assign for combinational logic.

Avoid using blocking assignments or single equals = inside assign.

Test your decoder by simulating input combinations to verify correct output activation.