How to Create VCD File in Verilog: Syntax and Example

To create a .vcd file in Verilog, use the system tasks $dumpfile to specify the file name and $dumpvars to start recording signal changes. Place these inside an initial block in your testbench to generate the VCD file during simulation.

Syntax

Use $dumpfile("filename.vcd") to set the output VCD file name. Then call $dumpvars(0, module_name) to record all signals in the specified module and its submodules. These calls are placed inside an initial block to run once at simulation start.

verilog

initial begin
  $dumpfile("output.vcd");  // Set VCD file name
  $dumpvars(0, testbench);    // Dump all signals from 'testbench' module
end

Example

This example shows a simple testbench that creates a VCD file named waveform.vcd capturing changes of a clock and reset signal.

verilog

module testbench;
  reg clk = 0;
  reg reset = 1;

  // Clock generation
  always #5 clk = ~clk;

  initial begin
    $dumpfile("waveform.vcd");
    $dumpvars(0, testbench);

    #10 reset = 0;  // Release reset after 10 time units
    #100 $finish;   // End simulation after 100 time units
  end
endmodule

Output

Simulation runs and creates waveform.vcd file with clk and reset signal changes.

Common Pitfalls

• Forgetting to call $dumpfile or $dumpvars results in no VCD file generated.
• Using incorrect module name in $dumpvars causes no signals to be recorded.
• Placing these calls outside an initial block can cause simulation errors.
• Not ending simulation with $finish may prevent VCD file from closing properly.

verilog

initial begin
  // Wrong: Missing $dumpfile call
  $dumpvars(0, testbench);
end

initial begin
  // Correct way
  $dumpfile("correct.vcd");
  $dumpvars(0, testbench);
end

Quick Reference

Command	Purpose
$dumpfile("file.vcd")	Set the name of the VCD output file
$dumpvars(level, module)	Start dumping variables from the module and submodules
$finish	End simulation and close VCD file
initial begin ... end	Place VCD commands inside to run once at simulation start

Key Takeaways

Use $dumpfile to specify the VCD file name before dumping variables.

Call $dumpvars inside an initial block to record signal changes.

Ensure the module name in $dumpvars matches your testbench or design module.

Always end simulation with $finish to properly close the VCD file.

Place all VCD-related commands inside an initial block to avoid errors.