Verilog Code for 2-to-4 Decoder: Syntax and Example

A 2-to-4 decoder in Verilog converts 2 input bits into 4 output lines, where only one output is active at a time. You can write it using an always block with a case statement or using continuous assignments with bitwise operations.

Syntax

The basic syntax for a 2-to-4 decoder uses an always block triggered by changes in the input bits. Inside, a case statement selects which output line to activate based on the input value. Outputs are usually declared as reg type because they are assigned inside always.

• input [1:0] in: 2-bit input signal
• output reg [3:0] out: 4-bit output signal, one-hot encoded
• always @(*): triggers on any input change
• case (in): selects output line

verilog

module decoder_2to4(input [1:0] in, output reg [3:0] out);
  always @(*) begin
    case (in)
      2'b00: out = 4'b0001;
      2'b01: out = 4'b0010;
      2'b10: out = 4'b0100;
      2'b11: out = 4'b1000;
      default: out = 4'b0000;
    endcase
  end
endmodule

Example

This example shows a complete 2-to-4 decoder module and a testbench that applies all input combinations. The testbench prints the input and output values to verify the decoder works correctly.

verilog

module decoder_2to4(input [1:0] in, output reg [3:0] out);
  always @(*) begin
    case (in)
      2'b00: out = 4'b0001;
      2'b01: out = 4'b0010;
      2'b10: out = 4'b0100;
      2'b11: out = 4'b1000;
      default: out = 4'b0000;
    endcase
  end
endmodule

module testbench();
  reg [1:0] in;
  wire [3:0] out;

  decoder_2to4 uut(.in(in), .out(out));

  initial begin
    $display("In  Out");
    for (integer i = 0; i < 4; i = i + 1) begin
      in = i;
      #1; // wait for output to settle
      $display("%b  %b", in, out);
    end
    $finish;
  end
endmodule

Output

In  Out
00  0001
01  0010
10  0100
11  1000

Common Pitfalls

Common mistakes when writing a 2-to-4 decoder include:

• Not using reg type for outputs assigned inside always blocks.
• Forgetting the default case, which can cause latches or unintended outputs.
• Using blocking assignments (=) incorrectly in sequential logic (though for combinational logic = is fine).
• Not covering all input cases, leading to simulation mismatches.

verilog

/* Wrong: output declared as wire and assigned in always block */
module wrong_decoder(input [1:0] in, output [3:0] out);
  always @(*) begin
    case (in)
      2'b00: out = 4'b0001; // Error: out is wire
      2'b01: out = 4'b0010;
      2'b10: out = 4'b0100;
      2'b11: out = 4'b1000;
    endcase
  end
endmodule

/* Correct: output declared as reg */
module correct_decoder(input [1:0] in, output reg [3:0] out);
  always @(*) begin
    case (in)
      2'b00: out = 4'b0001;
      2'b01: out = 4'b0010;
      2'b10: out = 4'b0100;
      2'b11: out = 4'b1000;
      default: out = 4'b0000;
    endcase
  end
endmodule

Quick Reference

Tips for writing a 2-to-4 decoder in Verilog:

• Use always @(*) for combinational logic.
• Declare outputs as reg if assigned inside always.
• Cover all input cases with case and include a default.
• Test with all input combinations to verify output correctness.

Key Takeaways

A 2-to-4 decoder activates one output line based on 2 input bits using a case statement.

Declare outputs as reg when assigning inside always blocks for combinational logic.

Always include a default case to avoid unintended latches or outputs.

Test all input combinations in a testbench to ensure correct decoder behavior.