How to Use Continuous Assignment in Verilog: Syntax and Examples

In Verilog, continuous assignment uses the assign keyword to drive values onto wire types continuously. It is used to model combinational logic by assigning expressions that update automatically when inputs change.

Syntax

The basic syntax of continuous assignment in Verilog is:

assign <wire_name> = <expression>;

Here, assign is the keyword that starts the continuous assignment. <wire_name> is the wire signal you want to drive, and <expression> is any valid combinational expression. This assignment updates automatically whenever any variable in the expression changes.

verilog

assign out = a & b;

Example

This example shows a simple AND gate using continuous assignment. The output out is always the AND of inputs a and b. When either input changes, out updates immediately.

verilog

module and_gate(
    input wire a,
    input wire b,
    output wire out
);

assign out = a & b;

endmodule

Common Pitfalls

1. Assigning to reg types: Continuous assignment only works with wire types. Trying to assign to reg with assign causes errors.

2. Multiple drivers: Avoid driving the same wire from multiple assign statements, as it causes conflicts.

3. Forgetting the semicolon: The assign statement must end with a semicolon.

verilog

/* Wrong: assigning to reg */
reg out_reg;
assign out_reg = a & b; // Error

/* Correct: use wire */
wire out_wire;
assign out_wire = a & b; // OK

Quick Reference

• assign drives wire signals continuously.
• Used for combinational logic expressions.
• Cannot assign to reg with assign.
• Always end with a semicolon.
• Multiple drivers on one wire cause errors.

Key Takeaways

Use assign to continuously drive wire signals with combinational logic.

Continuous assignments update automatically when inputs change.

Never assign to reg types using assign.

Avoid multiple continuous assignments driving the same wire.

Always end assign statements with a semicolon.