Verilog Code for Mod N Counter: Syntax and Example

A mod n counter in Verilog counts from 0 up to n-1 and then resets to 0. It uses a register to hold the count and an always block triggered by a clock to increment and reset the count when it reaches n-1.

Syntax

The basic syntax for a mod n counter in Verilog includes a register to hold the count, an always @(posedge clk or posedge reset) block to update the count on each clock pulse or reset, and a conditional statement to reset the count to zero when it reaches n-1.

• clk: Clock signal triggering count updates.
• reset: Asynchronous reset to set count to zero.
• count: Register holding the current count value.
• n: The modulus value defining the counter range (0 to n-1).

verilog

module mod_n_counter #(
    parameter n = 8
)(
    input wire clk,
    input wire reset,
    output reg [$clog2(n)-1:0] count
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            count <= 0;
        end else if (count == n-1) begin
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end
endmodule

Example

This example shows a mod 5 counter that counts from 0 to 4 and then resets to 0. It uses a clock and reset input. The output count updates on each clock pulse.

verilog

module mod_5_counter(
    input wire clk,
    input wire reset,
    output reg [2:0] count
);
    parameter n = 5;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            count <= 0;
        end else if (count == n-1) begin
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end
endmodule

// Testbench to simulate the mod 5 counter
module testbench();
    reg clk = 0;
    reg reset = 1;
    wire [2:0] count;

    mod_5_counter uut(.clk(clk), .reset(reset), .count(count));

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        $monitor($time, " ns: count = %d", count);
        #10 reset = 0; // Release reset after 10 ns
        #100 $finish;
    end
endmodule

Output

10 ns: count = 0
15 ns: count = 1
25 ns: count = 2
35 ns: count = 3
45 ns: count = 4
55 ns: count = 0
65 ns: count = 1
75 ns: count = 2
85 ns: count = 3
95 ns: count = 4

Common Pitfalls

Common mistakes when writing mod n counters include:

• Forgetting to reset the count to zero when it reaches n-1, causing overflow.
• Not using a wide enough register size for count, which can cause incorrect counting.
• Using synchronous reset but expecting asynchronous behavior or vice versa.
• Incorrectly calculating the bit width for the count register.

verilog

/* Wrong: No reset to zero at n-1, count keeps increasing */
always @(posedge clk or posedge reset) begin
    if (reset) count <= 0;
    else count <= count + 1; // No mod reset
end

/* Right: Reset count to zero at n-1 */
always @(posedge clk or posedge reset) begin
    if (reset) count <= 0;
    else if (count == n-1) count <= 0;
    else count <= count + 1;
end

Quick Reference

Tips for writing mod n counters in Verilog:

• Use parameter n to set the modulus value for easy changes.
• Calculate register width with $clog2(n) to fit the count range.
• Use asynchronous reset for immediate reset response.
• Always reset count to zero when it reaches n-1.

Key Takeaways

A mod n counter counts from 0 to n-1 and resets to 0 on reaching n-1.

Use a register sized with $clog2(n) bits to hold the count value.

Always reset the count to zero when it reaches n-1 to avoid overflow.

Use asynchronous reset for immediate clearing of the counter.

Parameterize n for easy reuse and modification of the counter range.