How to Use Primitive Gates in Verilog: Syntax and Examples

In Verilog, primitive gates like and, or, not, nand, nor, and xor are used by instantiating them with a name and connecting inputs and outputs using wires. You write the gate type followed by an instance name and then list the output and inputs in parentheses.

Syntax

Primitive gates in Verilog are instantiated using the gate type, an instance name, and a port list where the first port is the output and the following ports are inputs.

Example syntax:

gate_type instance_name (output, input1, input2, ...);

Here:

• gate_type: The type of gate like and, or, not, etc.
• instance_name: A unique name for this gate instance.
• output: The wire or net that receives the gate output.
• input1, input2, ...: The input wires to the gate.

verilog

and U1 (out, in1, in2);
not U2 (out_not, in1);

Example

This example shows how to use primitive gates to build a simple circuit where out_and is the AND of two inputs, out_or is the OR, and out_not is the NOT of one input.

verilog

module primitive_gates_example();
  reg in1, in2;
  wire out_and, out_or, out_not;

  and and_gate (out_and, in1, in2);
  or or_gate (out_or, in1, in2);
  not not_gate (out_not, in1);

  initial begin
    in1 = 0; in2 = 0;
    #10 $display("in1=%b in2=%b | AND=%b OR=%b NOT(in1)=%b", in1, in2, out_and, out_or, out_not);
    in1 = 0; in2 = 1;
    #10 $display("in1=%b in2=%b | AND=%b OR=%b NOT(in1)=%b", in1, in2, out_and, out_or, out_not);
    in1 = 1; in2 = 0;
    #10 $display("in1=%b in2=%b | AND=%b OR=%b NOT(in1)=%b", in1, in2, out_and, out_or, out_not);
    in1 = 1; in2 = 1;
    #10 $display("in1=%b in2=%b | AND=%b OR=%b NOT(in1)=%b", in1, in2, out_and, out_or, out_not);
  end
endmodule

Output

in1=0 in2=0 | AND=0 OR=0 NOT(in1)=1
in1=0 in2=1 | AND=0 OR=1 NOT(in1)=1
in1=1 in2=0 | AND=0 OR=1 NOT(in1)=0
in1=1 in2=1 | AND=1 OR=1 NOT(in1)=0

Common Pitfalls

• Forgetting that the first port is always the output, not an input.
• Using reg type for outputs of primitive gates instead of wire. Outputs must be wires.
• Not giving unique instance names for each gate.
• Confusing gate types or using unsupported gate names.

Example of wrong and right usage:

verilog

// Wrong: output declared as reg
module wrong_example();
  reg out;
  reg in1, in2;
  and and1 (out, in1, in2); // Error: output must be wire
endmodule

// Right:
module right_example();
  wire out;
  reg in1, in2;
  and and1 (out, in1, in2); // Correct
endmodule

Quick Reference

Gate Type	Description	Example
and	AND gate	and U1 (out, in1, in2);
or	OR gate	or U2 (out, in1, in2);
not	NOT gate (inverter)	not U3 (out, in);
nand	NAND gate	nand U4 (out, in1, in2);
nor	NOR gate	nor U5 (out, in1, in2);
xor	XOR gate	xor U6 (out, in1, in2);
xnor	XNOR gate	xnor U7 (out, in1, in2);

Key Takeaways

Primitive gates in Verilog are instantiated with gate type, instance name, and port list where the first port is output.

Outputs of primitive gates must be declared as wires, not regs.

Always give unique instance names to each gate to avoid conflicts.

Common gates include and, or, not, nand, nor, xor, and xnor.

Remember the order: output first, then inputs in the port list.