How to Write Synchronous Reset in Verilog: Syntax and Example

To write a synchronous reset in Verilog, include the reset signal inside the clocked always @(posedge clk) block and check the reset condition before other logic. This ensures the reset happens only on the clock edge, making it synchronous with the clock.

Syntax

The synchronous reset is written inside a clock-triggered always block. The reset signal is checked first, and if active, the registers are set to their reset values. Otherwise, normal logic runs.

• always @(posedge clk): Trigger block on rising clock edge.
• if (reset): Check if reset is active.
• Reset logic inside the if block sets registers to default.
• else block contains normal sequential logic.

verilog

always @(posedge clk) begin
    if (reset) begin
        // reset registers
    end else begin
        // normal logic
    end
end

Example

This example shows a simple 4-bit counter with a synchronous reset. When reset is high at the clock edge, the counter resets to 0. Otherwise, it increments by 1.

verilog

module sync_reset_counter(
    input wire clk,
    input wire reset,
    output reg [3:0] count
);

always @(posedge clk) begin
    if (reset) begin
        count <= 4'b0000; // reset counter to 0
    end else begin
        count <= count + 1; // increment counter
    end
end

endmodule

Output

At each rising clock edge, if reset=1, count=0; else count increments by 1.

Common Pitfalls

Common mistakes when writing synchronous reset include:

• Placing reset outside the clocked always block, making it asynchronous.
• Using blocking assignments (=) instead of non-blocking (<=) inside sequential logic.
• Not checking reset first, which can cause unexpected behavior.

verilog

/* Wrong: asynchronous reset */
always @(posedge clk or posedge reset) begin
    if (reset) count <= 0;
    else count <= count + 1;
end

/* Correct: synchronous reset */
always @(posedge clk) begin
    if (reset) count <= 0;
    else count <= count + 1;
end

Quick Reference

Concept	Description
Clock edge	Use always @(posedge clk) for synchronous logic
Reset check	Check if (reset) inside clocked block
Reset action	Set registers to default values inside reset block
Normal operation	Put normal logic inside else block
Assignment type	Use non-blocking <= for sequential assignments

Key Takeaways

Write synchronous reset inside an always block triggered only by the clock edge.

Check the reset signal first inside the clocked block to set registers to default.

Use non-blocking assignments (<=) for all sequential logic inside the always block.

Avoid mixing asynchronous reset signals with synchronous logic in the same block.

Synchronous reset ensures reset happens only on clock edges, improving timing control.