How to Write Your First Verilog Program: Simple Guide

To write your first Verilog program, start by defining a module with inputs and outputs. Inside the module, use assign statements or procedural blocks to describe hardware behavior. Finally, save the code in a .v file and simulate it with a Verilog tool.

Syntax

A basic Verilog program starts with a module declaration that names the hardware block and lists its inputs and outputs. Inside the module, you describe the logic using assign for simple connections or always blocks for sequential logic. The module ends with endmodule.

• module: Defines the hardware block.
• input: Declares input signals.
• output: Declares output signals.
• assign: Connects signals with combinational logic.
• endmodule: Ends the module definition.

verilog

module simple_and_gate(input a, input b, output y);
  assign y = a & b;
endmodule

Example

This example shows a simple AND gate module that takes two inputs and produces one output. It demonstrates how to declare inputs and outputs and use an assign statement for combinational logic.

verilog

module and_gate(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

Output

When simulated, output y is 1 only if both inputs a and b are 1; otherwise, y is 0.

Common Pitfalls

Beginners often forget to declare inputs and outputs properly or miss the endmodule keyword. Another common mistake is using = inside modules instead of assign for combinational logic. Also, mixing blocking (=) and non-blocking (<=) assignments incorrectly can cause simulation errors.

Wrong example (missing assign):

module wrong(input a, input b, output y);
  y = a & b; // Error: should use assign
endmodule

Correct example:

module correct(input a, input b, output y);
  assign y = a & b;
endmodule

Quick Reference

Keyword	Purpose
module	Start a hardware block definition
input	Declare input signals
output	Declare output signals
assign	Create combinational logic connections
endmodule	End the module definition

Key Takeaways

Start every Verilog program with a module that declares inputs and outputs.

Use assign statements for simple combinational logic inside modules.

Always end your module with endmodule to avoid syntax errors.

Avoid using = inside modules without assign; use assign for combinational logic.

Check your signal declarations carefully to prevent common mistakes.