VerilogHow-ToBeginner · 3 min read

Verilog Code for 4 Bit Up Counter: Syntax and Example

A 4 bit up counter in Verilog counts from 0 to 15 using a 4-bit register that increments on each clock pulse. Use always @(posedge clk or posedge reset) to update the count and reset it to zero when needed.

📐

Syntax

The basic syntax for a 4 bit up counter uses an always block triggered on the rising edge of the clock or reset signal. Inside, the counter increments by 1 on each clock pulse and resets to zero when the reset is high.

input clk: Clock signal to trigger counting.
input reset: Resets the counter to zero when high.
output reg [3:0] count: 4-bit register holding the current count.

verilog

module up_counter_4bit(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 4'b0000;
    else
        count <= count + 1;
end

endmodule

💻

Example

This example shows a complete 4 bit up counter module that increments the count on each clock pulse and resets to zero when the reset signal is high.

verilog

module up_counter_4bit(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 4'b0000;
    else
        count <= count + 1;
end

endmodule

// Testbench to simulate the counter
module testbench();
    reg clk = 0;
    reg reset = 0;
    wire [3:0] count;

    up_counter_4bit uut(.clk(clk), .reset(reset), .count(count));

    // Clock generation
    always #5 clk = ~clk; // 10 time units period

    initial begin
        $monitor($time, " clk=%b reset=%b count=%b", clk, reset, count);
        reset = 1; #10;
        reset = 0; #100;
        $finish;
    end
endmodule

Output

0 clk=0 reset=1 count=0000 5 clk=1 reset=1 count=0000 10 clk=0 reset=0 count=0000 15 clk=1 reset=0 count=0001 25 clk=1 reset=0 count=0010 35 clk=1 reset=0 count=0011 45 clk=1 reset=0 count=0100 55 clk=1 reset=0 count=0101 65 clk=1 reset=0 count=0110 75 clk=1 reset=0 count=0111 85 clk=1 reset=0 count=1000 95 clk=1 reset=0 count=1001 105 clk=1 reset=0 count=1010 115 clk=1 reset=0 count=1011 125 clk=1 reset=0 count=1100 135 clk=1 reset=0 count=1101 145 clk=1 reset=0 count=1110 155 clk=1 reset=0 count=1111 165 clk=1 reset=0 count=0000

⚠️

Common Pitfalls

Common mistakes when writing a 4 bit up counter include:

Forgetting to reset the counter, causing it to start at an unknown value.
Using blocking assignments (=) instead of non-blocking (<=) inside the always block, which can cause simulation mismatches.
Not including the reset signal in the sensitivity list, so the counter does not reset properly.

verilog

/* Wrong: Using blocking assignment and missing reset in sensitivity list */
module wrong_counter(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk) begin
    if (reset)
        count = 4'b0000; // blocking assignment - wrong
    else
        count = count + 1; // blocking assignment - wrong
end

endmodule

/* Correct: Using non-blocking assignment and including reset */
module correct_counter(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 4'b0000; // non-blocking assignment
    else
        count <= count + 1;
end

endmodule

📊

Quick Reference

Remember these tips when creating a 4 bit up counter in Verilog:

Use always @(posedge clk or posedge reset) for synchronous counting with asynchronous reset.
Use non-blocking assignments (<=) inside always blocks.
Initialize or reset the counter to avoid unknown start values.
Count increments by adding 1 to the current count.

✅

Key Takeaways

Use an always block triggered on clock and reset edges for synchronous counting.

Reset the counter to zero to avoid unknown initial values.

Use non-blocking assignments (<=) inside always blocks for correct simulation.

Increment the 4-bit register by 1 on each clock pulse to count up.

Include reset in the sensitivity list to ensure proper reset behavior.