How to Use ILA for Debugging FPGA in Verilog

To debug FPGA designs in Verilog using ILA, instantiate the ILA core in your design, connect signals you want to monitor, and configure triggers in your FPGA tool. The ILA captures internal signal data during FPGA operation, which you can view in real-time using vendor software like Vivado.

Syntax

The ILA core is instantiated as a module in your Verilog design. You connect the signals you want to monitor to its probe ports. The basic syntax includes the ILA instance with parameters for probe width and clock input.

• clk: Clock signal for sampling probes.
• probe0, probe1, ...: Signals to monitor inside FPGA.
• probe_width: Width of each probe signal.

verilog

ila_0 ila_inst (
    .clk(clk),          // Clock input
    .probe0(signal_a),  // First signal to monitor
    .probe1(signal_b)   // Second signal to monitor
);

Example

This example shows how to instantiate an ILA core to monitor two internal signals counter and flag in a simple counter module. The ILA captures these signals on the clock for debugging.

verilog

module counter_with_ila(
    input wire clk,
    input wire rst,
    output reg [3:0] counter
);

wire flag = (counter == 4'd10);

// Instantiate ILA core
ila_0 ila_inst (
    .clk(clk),
    .probe0(counter),
    .probe1(flag)
);

always @(posedge clk or posedge rst) begin
    if (rst) 
        counter <= 4'd0;
    else 
        counter <= counter + 1'b1;
end

endmodule

Common Pitfalls

• Not connecting the clock: The ILA needs a clock input to sample signals; forgetting this causes no data capture.
• Incorrect probe widths: Probe widths must match the signal widths exactly or cause synthesis errors.
• Not enabling ILA in constraints: You must enable and configure the ILA core in your FPGA tool (e.g., Vivado) for it to work.
• Expecting ILA to work without FPGA programming: The FPGA must be programmed with the ILA-enabled bitstream to capture data.

verilog

/* Wrong: Missing clock connection */
ila_0 ila_inst_wrong (
    .probe0(signal_a)
);

/* Right: Include clock */
ila_0 ila_inst_right (
    .clk(clk),
    .probe0(signal_a)
);

Quick Reference

Tips for using ILA:

• Instantiate ILA with clock and probes connected.
• Match probe widths to signal widths exactly.
• Configure triggers and capture settings in FPGA vendor software.
• Program FPGA with ILA-enabled bitstream before debugging.
• Use Vivado Hardware Manager or similar tool to view captured waveforms.

Key Takeaways

Always connect the clock signal to the ILA core for proper sampling.

Match probe widths exactly to the signals you want to monitor.

Configure and enable the ILA core in your FPGA tool before programming.

Use vendor software like Vivado Hardware Manager to view captured data.

ILA captures internal FPGA signals in real-time without extra hardware.