How to Do Timing Analysis in FPGA Using Verilog

To do timing analysis in FPGA with Verilog, first write your RTL code and synthesize it using FPGA vendor tools like Vivado or Quartus. Then run the static timing analysis (STA) tool provided by the vendor to check if your design meets timing constraints such as clock period and setup/hold times.

Syntax

Timing analysis itself is not done directly in Verilog code but through FPGA tools after synthesis. However, you specify timing constraints in a separate constraints file (like .xdc for Vivado or .sdc for Quartus) using commands such as:

• create_clock: Defines the clock period.
• set_input_delay and set_output_delay: Specify delays for input/output ports.
• set_max_delay: Sets maximum delay between signals.

These constraints guide the timing analysis tools to verify your design meets timing requirements.

tcl

create_clock -period 10.0 -name clk [get_ports clk]
set_input_delay -clock clk 2.0 [get_ports data_in]
set_output_delay -clock clk 2.0 [get_ports data_out]

Example

This example shows a simple Verilog module with a clock and a flip-flop, plus a timing constraint file snippet for a 10 ns clock period. After synthesis, run the timing analysis tool to check if the design meets the 10 ns clock period.

verilog

module simple_ff(
  input wire clk,
  input wire d,
  output reg q
);

  always @(posedge clk) begin
    q <= d;
  end

endmodule

// Timing constraints file (example.xdc for Vivado):
// create_clock -period 10.0 -name clk [get_ports clk]

Output

Timing report shows all paths meet the 10 ns clock period requirement.

Common Pitfalls

Common mistakes when doing timing analysis in FPGA include:

• Not defining clocks properly in the constraints file, causing the tool to miss timing checks.
• Ignoring input/output delays, which can lead to false timing violations.
• Using asynchronous resets or signals without proper timing constraints.
• Not running timing analysis after synthesis and implementation steps.

Always verify your constraints and run the timing report to catch issues early.

tcl

## Wrong: No clock defined
# No create_clock command in constraints file

## Right: Define clock
create_clock -period 10.0 -name clk [get_ports clk]

Quick Reference

Command	Purpose
create_clock	Defines the clock period and name
set_input_delay	Sets delay for input ports relative to clock
set_output_delay	Sets delay for output ports relative to clock
set_max_delay	Sets maximum allowed delay between signals
report_timing	Generates timing analysis report

Key Takeaways

Define clocks and timing constraints clearly in your constraints file before analysis.

Use FPGA vendor tools like Vivado or Quartus to run static timing analysis after synthesis.

Check timing reports to ensure all paths meet setup and hold time requirements.

Include input and output delays to model real-world signal timing accurately.

Fix timing violations by adjusting your design or constraints and rerun analysis.