Verilog Code for JK Flip Flop: Syntax and Example

A JK flip flop in Verilog can be coded using an always block triggered on the clock's rising edge, with inputs J, K, and output Q. The flip flop toggles, sets, resets, or holds the output based on the values of J and K inputs.

Syntax

The JK flip flop is described inside an always @(posedge clk) block to update output Q on the clock's rising edge. Inputs J and K control the state changes:

• J=0, K=0: No change
• J=0, K=1: Reset output to 0
• J=1, K=0: Set output to 1
• J=1, K=1: Toggle output

verilog

module jk_flip_flop(
    input wire clk,
    input wire J,
    input wire K,
    output reg Q
);

always @(posedge clk) begin
    case ({J, K})
        2'b00: Q <= Q;        // No change
        2'b01: Q <= 1'b0;    // Reset
        2'b10: Q <= 1'b1;    // Set
        2'b11: Q <= ~Q;      // Toggle
    endcase
end

endmodule

Example

This example shows a JK flip flop module with a clock, J and K inputs, and output Q. The testbench toggles inputs and clock to demonstrate the flip flop behavior.

verilog

module jk_flip_flop(
    input wire clk,
    input wire J,
    input wire K,
    output reg Q
);

always @(posedge clk) begin
    case ({J, K})
        2'b00: Q <= Q;
        2'b01: Q <= 1'b0;
        2'b10: Q <= 1'b1;
        2'b11: Q <= ~Q;
    endcase
end

endmodule

// Testbench
module testbench();
    reg clk = 0;
    reg J = 0;
    reg K = 0;
    wire Q;

    jk_flip_flop uut(.clk(clk), .J(J), .K(K), .Q(Q));

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        $monitor($time, ": J=%b K=%b Q=%b", J, K, Q);

        // Test sequence
        J = 0; K = 0; #10; // No change
        J = 1; K = 0; #10; // Set Q=1
        J = 0; K = 1; #10; // Reset Q=0
        J = 1; K = 1; #10; // Toggle Q=1
        J = 1; K = 1; #10; // Toggle Q=0
        J = 0; K = 0; #10; // No change

        $finish;
    end
endmodule

Output

0: J=0 K=0 Q=x
10: J=1 K=0 Q=1
20: J=0 K=1 Q=0
30: J=1 K=1 Q=1
40: J=1 K=1 Q=0
50: J=0 K=0 Q=0

Common Pitfalls

Common mistakes include:

• Not using posedge clk causing incorrect timing.
• Forgetting to declare Q as reg type.
• Using blocking assignments (=) instead of non-blocking (<=) inside the always block.
• Not handling the toggle case properly, which should invert Q.

verilog

/* Wrong way: Using blocking assignment and missing posedge */
module wrong_jk(
    input wire clk,
    input wire J,
    input wire K,
    output reg Q
);

always @(clk) begin
    if (J == 1 && K == 1)
        Q = ~Q; // Blocking assignment causes glitches
end

endmodule

/* Right way: Use posedge and non-blocking assignment */
module right_jk(
    input wire clk,
    input wire J,
    input wire K,
    output reg Q
);

always @(posedge clk) begin
    if (J == 1 && K == 1)
        Q <= ~Q; // Non-blocking assignment
end

endmodule

Quick Reference

JK Flip Flop Input-Output Behavior:

J	K	Output Q (next state)
0	0	No change (Q)
0	1	Reset (0)
1	0	Set (1)
1	1	Toggle (~Q)

Key Takeaways

Use an always block triggered on posedge clk to model JK flip flop behavior.

Use non-blocking assignments (<=) inside always blocks for correct simulation.

Declare output Q as reg type to hold state.

Handle all JK input combinations explicitly to avoid unexpected output.

Test your flip flop with a testbench toggling inputs and clock.