VerilogHow-ToBeginner · 3 min read

How to Use $dumpfile and $dumpvars in Verilog for Waveform Dumping

In Verilog, use $dumpfile to specify the name of the waveform dump file and $dumpvars to start dumping variable changes into that file during simulation. These system tasks help you generate waveform files (usually .vcd) to visually debug your design.

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Syntax

$dumpfile("filename.vcd"); sets the output file name for the waveform dump. $dumpvars(level, module_instance); starts dumping variables from the specified module instance and its sub-modules. The level controls how deep the dumping goes in the hierarchy (0 means the specified module and all its sub-modules, higher numbers can be used for more control).

verilog

$dumpfile("waveform.vcd");
$dumpvars(0, testbench);

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Example

This example shows how to use $dumpfile and $dumpvars in a simple testbench to create a waveform file named test.vcd. The waveform file can be opened with a viewer to see signal changes over time.

verilog

module testbench;
  reg clk = 0;
  reg reset = 1;

  // Clock generation
  always #5 clk = ~clk;

  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, testbench);

    #10 reset = 0;
    #100 $finish;
  end
endmodule

Output

Simulation runs and creates a file named test.vcd with signal changes for clk and reset.

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Common Pitfalls

Forgetting to call $dumpfile before $dumpvars causes no file to be created.
Using $dumpvars without specifying the correct module instance may dump no signals or too many signals.
Not calling $finish ends simulation without closing the dump file properly.
Using a wrong file extension or path can cause the waveform viewer to fail loading the file.

verilog

/* Wrong way: Missing $dumpfile */
initial begin
  $dumpvars(0, testbench);
  #10 $finish;
end

/* Right way: */
initial begin
  $dumpfile("correct.vcd");
  $dumpvars(0, testbench);
  #10 $finish;
end

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Quick Reference

Command	Purpose	Example
$dumpfile	Sets the waveform dump file name	$dumpfile("output.vcd");
$dumpvars	Starts dumping variables to the file	$dumpvars(0, top_module);
$finish	Ends simulation and closes dump file	$finish;

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Key Takeaways

Always call $dumpfile before $dumpvars to specify the dump file name.

$dumpvars controls which signals and hierarchy levels are dumped for waveform viewing.

Use $finish to properly end simulation and close the dump file.

Waveform files (.vcd) help visually debug signal changes during simulation.

Specify the correct module instance in $dumpvars to capture desired signals.