How to Write Task in Verilog: Syntax and Example

In Verilog, a task is a reusable block of code that can perform actions and be called from procedural blocks. You write a task using the task keyword, define its inputs and outputs if needed, and end it with endtask. Tasks help organize code and avoid repetition.

Syntax

A task in Verilog is defined with the task keyword followed by the task name. You can declare input, output, and inout arguments inside parentheses. The task body contains the statements to execute. It ends with endtask.

• task_name: The name used to call the task.
• input/output/inout: Optional arguments to pass data in or out.
• begin ... end: Group multiple statements inside the task.

verilog

task task_name;
  input [7:0] in_val;
  output reg [7:0] out_val;
  begin
    // task statements
  end
endtask

Example

This example shows a task named increment that takes an 8-bit input and returns the input value plus one as output. The task is called inside an initial block to demonstrate usage.

verilog

module test_task;
  reg [7:0] a, b;

  // Define the task
  task increment;
    input [7:0] in_val;
    output reg [7:0] out_val;
    begin
      out_val = in_val + 1;
    end
  endtask

  initial begin
    a = 8'd10;
    increment(a, b); // call the task
    $display("Input: %d, Output after increment: %d", a, b);
  end
endmodule

Output

Input: 10, Output after increment: 11

Common Pitfalls

Common mistakes when writing tasks include:

• Forgetting to declare output or inout arguments as reg inside the task.
• Calling tasks outside procedural blocks like initial or always.
• Using tasks for combinational logic instead of functions (tasks can have delays and multiple statements).

Here is an example showing a wrong and right way to declare outputs:

verilog

// Wrong: output not declared as reg
// task wrong_task;
//   output out_val;
//   begin
//     out_val = 1'b1; // error: out_val must be reg
//   end
// endtask

// Right way:
task right_task;
  output reg out_val;
  begin
    out_val = 1'b1; // correct
  end
endtask

Quick Reference

Remember these tips when using tasks in Verilog:

• Use task and endtask to define a task.
• Declare inputs and outputs inside the task header.
• Outputs must be declared as reg inside the task.
• Call tasks only inside procedural blocks like initial or always.
• Use tasks for actions that may include delays or multiple statements.

Key Takeaways

Define tasks with task and endtask keywords including input/output arguments.

Outputs inside tasks must be declared as reg to hold values.

Call tasks only inside procedural blocks like initial or always.

Use tasks for multi-statement operations or those involving delays, not for pure combinational logic.

Tasks help organize and reuse code by grouping related statements.