How to Model OR Gate in Verilog: Syntax and Example

In Verilog, you can model an OR gate using the or gate primitive or by using the | operator in an assign statement. The or gate primitive connects inputs to an output, while the assign statement uses bitwise OR to combine signals.

Syntax

The OR gate in Verilog can be modeled using the or gate primitive or an assign statement.

• Gate primitive syntax: or (output, input1, input2, ...); connects inputs to output with OR logic.
• Assign statement syntax: assign output = input1 | input2; uses bitwise OR operator.

verilog

or (Y, A, B);  // Gate primitive example
assign Y = A | B; // Assign statement example

Example

This example shows how to model a 2-input OR gate using both the gate primitive and assign statement. It demonstrates the output for all input combinations.

verilog

module or_gate_example();
  reg A, B;
  wire Y1, Y2;

  // Using gate primitive
  or or1(Y1, A, B);

  // Using assign statement
  assign Y2 = A | B;

  initial begin
    $display("A B | Y1 Y2");
    A = 0; B = 0; #10 $display("%b %b |  %b  %b", A, B, Y1, Y2);
    A = 0; B = 1; #10 $display("%b %b |  %b  %b", A, B, Y1, Y2);
    A = 1; B = 0; #10 $display("%b %b |  %b  %b", A, B, Y1, Y2);
    A = 1; B = 1; #10 $display("%b %b |  %b  %b", A, B, Y1, Y2);
    $finish;
  end
endmodule

Output

A B | Y1 Y2
0 0 |  0  0
0 1 |  1  1
1 0 |  1  1
1 1 |  1  1

Common Pitfalls

Common mistakes when modeling OR gates in Verilog include:

• Using or as a variable name, which conflicts with the gate primitive keyword.
• Forgetting to declare inputs as reg and outputs as wire when using gate primitives.
• Using blocking assignments (=) inside always blocks incorrectly for combinational logic instead of continuous assignments or proper always blocks.

verilog

/* Wrong: Using 'or' as variable name */
// reg or; // This causes syntax error

/* Correct: Use different variable name */
reg a, b;
wire y;
or or1(y, a, b);

Quick Reference

Concept	Syntax	Description
OR gate primitive	or (Y, A, B);	Connects inputs A, B to output Y with OR logic
Assign statement	assign Y = A | B;	Uses bitwise OR operator for output Y
Input declaration	reg A, B;	Inputs declared as reg for testbench signals
Output declaration	wire Y;	Output declared as wire for gate output

Key Takeaways

Use the 'or' gate primitive or 'assign' with '|' operator to model OR gates in Verilog.

Declare inputs as reg and outputs as wire when using gate primitives.

Avoid using 'or' as a variable name to prevent syntax errors.

Continuous assignments with 'assign' are preferred for simple combinational logic.

Test all input combinations to verify correct OR gate behavior.