Mealy vs Moore Machine in Verilog: Key Differences and Code Examples

A Mealy machine produces outputs based on the current state and inputs, making outputs change immediately with inputs. A Moore machine produces outputs based only on the current state, so outputs change only on state transitions. In Verilog, this difference affects how you write the output logic inside or outside the state register block.

Quick Comparison

Here is a quick side-by-side comparison of Mealy and Moore machines in Verilog.

Factor	Mealy Machine	Moore Machine
Output depends on	Current state and inputs	Current state only
Output timing	Can change asynchronously with inputs	Changes synchronously on state changes
Output logic location	Inside combinational block with inputs	Inside state register or separate block
State complexity	Usually fewer states	Usually more states
Output glitches	Possible due to input changes	Less prone to glitches
Typical use case	Faster response to inputs	Simpler and more stable outputs

Key Differences

A Mealy machine generates outputs based on both the current state and the current inputs. This means the output can change immediately when inputs change, even between clock edges. In Verilog, this is usually implemented by assigning outputs in a combinational block that depends on inputs and state.

In contrast, a Moore machine generates outputs solely based on the current state. Outputs only change when the state changes, typically synchronized with the clock. This makes the output more stable and less prone to glitches. In Verilog, outputs are assigned based on the state register, often in a sequential block or a separate combinational block that depends only on the state.

Because Mealy machines react faster to inputs, they can be more efficient but may cause glitches if inputs change asynchronously. Moore machines are simpler to design and debug due to their stable outputs but may require more states to represent the same behavior.

Code Comparison

Below is a simple example of a Mealy machine in Verilog that outputs 1 when input x is 1 and the state is 0.

verilog

module mealy_fsm(
    input clk,
    input reset,
    input x,
    output reg z
);

    typedef enum reg [1:0] {S0, S1} state_t;
    state_t state, next_state;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case(state)
            S0: next_state = x ? S1 : S0;
            S1: next_state = x ? S1 : S0;
            default: next_state = S0;
        endcase
    end

    // Output logic (depends on state and input)
    always @(*) begin
        case(state)
            S0: z = x;      // Output depends on input x
            S1: z = 0;
            default: z = 0;
        endcase
    end

endmodule

Moore Equivalent

Here is the equivalent Moore machine where output z depends only on the state.

verilog

module moore_fsm(
    input clk,
    input reset,
    input x,
    output reg z
);

    typedef enum reg [1:0] {S0, S1} state_t;
    state_t state, next_state;

    // State transition
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case(state)
            S0: next_state = x ? S1 : S0;
            S1: next_state = x ? S1 : S0;
            default: next_state = S0;
        endcase
    end

    // Output logic (depends only on state)
    always @(*) begin
        case(state)
            S0: z = 0;
            S1: z = 1;      // Output depends only on state
            default: z = 0;
        endcase
    end

endmodule

When to Use Which

Choose a Mealy machine when you need faster output response to input changes and can handle potential glitches. It is useful in designs where output must react immediately without waiting for a clock edge.

Choose a Moore machine when output stability and simplicity are more important. Moore machines are easier to debug and less prone to glitches, making them suitable for control logic where outputs should change only on state transitions.

Key Takeaways

Mealy outputs depend on state and inputs, changing immediately with inputs.

Moore outputs depend only on state, changing synchronously on state changes.

Mealy machines can be faster but may cause glitches; Moore machines are more stable.

In Verilog, Mealy output logic includes inputs; Moore output logic depends only on state.

Choose Mealy for speed, Moore for simplicity and stable outputs.