What is Sensitivity List in Verilog: Explanation and Example

In Verilog, a sensitivity list is a list of signals that trigger the execution of an always block when they change. It tells the simulator which signals to watch so the block runs only when needed, making the design efficient and accurate.

How It Works

Think of a sensitivity list like a watchlist for a security guard. The guard only reacts when something on the watchlist changes. In Verilog, the always block has a sensitivity list that tells it which signals to "watch." When any signal in this list changes value, the block runs its code.

This helps the simulation run faster and behave correctly because the block doesn't run all the time, only when important signals change. For example, if you want to update a value whenever a clock or reset signal changes, you put those signals in the sensitivity list.

Example

This example shows an always block with a sensitivity list that includes clk and reset. The block runs only when clk or reset changes.

verilog

module sensitivity_example(input clk, input reset, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) 
      q <= 0;
    else 
      q <= ~q;
  end
endmodule

When to Use

Use a sensitivity list in always blocks to specify exactly which signals should trigger the block. This is important for modeling combinational or sequential logic correctly.

For example, in sequential logic like flip-flops, you include the clock and reset signals in the sensitivity list. For combinational logic, you include all input signals that affect the output. This ensures your design updates only when necessary, avoiding simulation errors and improving performance.

Key Points

• The sensitivity list controls when an always block runs.
• It includes signals that the block "listens" to for changes.
• Proper sensitivity lists prevent simulation mismatches and improve efficiency.
• For combinational logic, include all inputs; for sequential logic, include clock and reset.

Key Takeaways

A sensitivity list tells an always block which signals to watch for changes.

It ensures the block runs only when needed, improving simulation accuracy and speed.

Include all relevant signals in the sensitivity list to model logic correctly.

Use clock and reset signals in sequential logic sensitivity lists.

For combinational logic, include all input signals affecting outputs.