How to Use PLL in FPGA with Verilog: Simple Guide

To use a PLL in an FPGA with Verilog, instantiate the vendor-specific PLL module in your design and connect the input clock and output clocks properly. You usually configure the PLL using FPGA tools to set multiplication and division factors, then use the generated module in your Verilog code.

Syntax

A PLL in FPGA is typically used by instantiating a vendor-specific module generated by FPGA tools. The basic syntax involves connecting the input clock, reset, and output clocks.

Key parts:

• input clock: The clock signal you want to modify.
• reset: Resets the PLL.
• output clocks: The new clocks generated by the PLL with desired frequency.

verilog

pll_module pll_inst (
    .clk_in(clk_in),       // Input clock
    .reset(reset),         // Reset signal
    .clk_out(clk_out),     // Output clock
    .locked(locked)        // PLL lock status
);

Example

This example shows how to instantiate a PLL module generated by FPGA tools (like Intel Quartus or Xilinx Vivado). The PLL multiplies the input clock frequency by 2.

verilog

module top_module(
    input wire clk_in,
    input wire reset,
    output wire clk_out,
    output wire locked
);

// Instantiate the PLL module
pll_module pll_inst (
    .clk_in(clk_in),
    .reset(reset),
    .clk_out(clk_out),
    .locked(locked)
);

endmodule

Common Pitfalls

Common mistakes when using PLLs in FPGA with Verilog include:

• Not using the vendor's PLL generator tool to create the correct PLL module.
• Forgetting to connect the locked signal to ensure the PLL is stable before using the output clock.
• Using the PLL output clock without proper buffering or constraints in the FPGA design.
• Ignoring the reset signal or not handling it correctly.

Always check your FPGA vendor documentation for the exact PLL instantiation and parameters.

verilog

/* Wrong way: Using a PLL without checking lock */
pll_module pll_inst (
    .clk_in(clk_in),
    .reset(reset),
    .clk_out(clk_out),
    .locked() // Not connected
);

/* Right way: Use locked signal to gate logic or wait for PLL lock */
wire pll_locked;
pll_module pll_inst2 (
    .clk_in(clk_in),
    .reset(reset),
    .clk_out(clk_out),
    .locked(pll_locked)
);

// Use pll_locked to enable downstream logic

Quick Reference

Tips for using PLLs in FPGA with Verilog:

• Always generate PLL modules using your FPGA vendor's tools.
• Connect and monitor the locked signal before using output clocks.
• Use proper clock constraints in your FPGA project for the PLL clocks.
• Reset the PLL properly to avoid unstable clocks.

Key Takeaways

Use your FPGA vendor's PLL generator tool to create the correct PLL module for your design.

Always connect and check the PLL's locked signal before using the output clock.

Properly reset the PLL and handle its reset input in your Verilog code.

Apply correct clock constraints and buffering for PLL output clocks in your FPGA project.